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Weltrend Semiconductor, Inc.
WT6573F
USB Device Controller with 16KB Flash
Data Sheet
Rev. 1.31
July 31, 2009
The information in this document is subject to change without notice. ∏Weltrend Semiconductor, Inc. All Rights Reserved.
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WT6573F
Data Sheet Rev. 1.31
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Data Sheet Rev. 1.31
1. Introduction............................................................................................................................................1
1.1 General Description......................................................................................................................1 1.2 Features........................................................................................................................................1 1.3 Ordering Information.....................................................................................................................2 2. Pin Assignment and Package Types.....................................................................................................3
2.1 Description....................................................................................................................................3 2.2 Package Pin Configuration...........................................................................................................5 2.3 Package Outline Dimension.........................................................................................................7 2.4 Pad Diagram and Location Table...............................................................................................12 3. Functional Description.........................................................................................................................14
3.1 USB Module................................................................................................................................14 3.2 Micro-controller...........................................................................................................................14 3.3 Address Space Mapping.............................................................................................................15
3.3.1 Special Function Register Address Space.......................................................................16 3.3.2 External Function Register Address Space......................................................................17 3.4 Clock Unit...................................................................................................................................18 3.5 Reset..........................................................................................................................................19 3.6 Power-down Mode and Idle Mode..............................................................................................19 3.7 Interrupt Table............................................................................................................................20 3.8 Function Endpoint.......................................................................................................................20 3.9 Transmit FIFOs...........................................................................................................................21
3.9.1 Transmit FIFOs Features.................................................................................................21 3.9.2 Transmit Data Set Management......................................................................................21 3.9.3 Transmit FIFO Registers..................................................................................................22 3.10 Receive FIFOs..........................................................................................................................23
3.10.1 Receive FIFO Features..................................................................................................23 3.10.2 Receive Data Set Management.....................................................................................24 3.10.3 Receive FIFO Registers.................................................................................................24 3.11 Setup Token Receive FIFO Handling.......................................................................................25 3.12 Suspend and Resume..............................................................................................................25 4. External Function Registers (XFR)......................................................................................................27
4.1 USB............................................................................................................................................27 4.2 Interrupt, Watch-dog, PWM, Ports, ADC XFR Definition...........................................................28 5. Register Descriptions...........................................................................................................................29
5.1 USB Related Registers...............................................................................................................29 5.2 Interrupt, Watch-dog, PWM, Ports, ADC Registers...................................................................45 5.3 SPI SFR......................................................................................................................................56 5.4 UART 115200/230400 Baud Rate..............................................................................................58 6. Application Circuits..............................................................................................................................59
6.1 Case 1: Only USB or 5V-power-supply is used:.........................................................................59 6.2 Case 2: Only Battery (<3.6V) is used:........................................................................................59 6.3 Case 3: Both USB and Battery are used:...................................................................................60 7. Electrical Characteristics......................................................................................................................61
7.1 Absolute Maximum Ratings........................................................................................................61 7.2 D.C. Characteristics....................................................................................................................61
Table of Contents
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Data Sheet Rev. 1.31
1. Introduction
1.1 General Description
WT6573F is a USB full speed / low speed device controller with Turbo 8052 CPU, 16K-byte Flash ROM, 512-byte SRAM, 19-channel 12-bit ADC, 2-channel 8-bit PWM, standard RS232 interface, SPI
2
master/slave interface, In-System-Programming (ISP) function by USB or IC interface, and on-chip ICE.
WT6573F is suitable for the USB peripheral applications, such as: PS3 game pad/joystick, USB game controller, USB MIDI keyboard, USB touch-pad, or any USB devices with ADC applications.
When USB-related circuit and V33 regulator are disabled, WT6573F could be used for portable applications which are powered by battery (VBAT <= 3.6V).
1.2 Features
8-bit Turbo 8052 compatible CPU with 24MHz operating frequency 12MHz or 24MHz crystal oscillator (selectable by S/W) 32kHz RC Ring Clock for off line and low power mode 16K bytes Flash ROM including EEPROM emulation
All pages of Flash ROM could be used (by page) as data storage Each page is 512-byte
512 bytes SRAM
USB features:
Complete compatible with Universal Serial Bus specification 2.0 Full / Low Speed 1 control endpoint, IN/OUT each with 64 Bytes (8/16/32/64-byte programmable) FIFO
3 Generic endpoints (IN/OUT INT/Bulk programmable) each with 64-Byte (8/16/32/64 bytes
programmable) FIFO; Endpoint 3 can also be configured as OUT token for endpoint 1 or 2 Supports USB Suspend, Resume and Remote Wakeup 19-channel 12-bit ADC with external reference voltage input 2-ch 8-bit PWM output
Idle and power down modes supported
Standard RS232 data transmission: up to 230400bps 1 SPI interface
Master/Slave mode selectable Max speed: 2MHz
Data length per transaction: 1-byte
45(max.) GPIO pins for chip form and LQFP64; 37(max.) GPIO pins for LQFP48; 29(max.) GPIO pins for QFN40; 21(max.) GPIO pins for QFN32
USB-related circuit and V33 voltage regulator can be disabled for portable applications which are powered by battery (VBAT <= 3.6V)
16 high sink current IO for LED control: Port A and Port E
IO falling edge detect interrupt, can work as wakeup trigger at the power down mode: Port A Three 16-bit timer/counter
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On-chip ICE Operating voltage:
Whole system (except USB and regulator) working voltage: 2.4V ~ 3.6V (from VBAT pin) USB and regulator working voltage: 4.0 ~ 5.25V (from VDD5V pin) Please refer to Chapter 6 (Application Circuits) for versatile applications
Watch-dog timer (10ms ~ 640ms programmable)
ISP function by 6-pin IC (VDD5V, VSS, OSCI, RESETN, SCL, SDA pins) or USB interface
2
Data Sheet Rev. 1.31
LQFP64(10x10, 7x7), LQFP48(7x7), QFN40(6x6), QFN32(5x5) and Chip form
1.3 Ordering Information
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Data Sheet Rev. 1.31
2. Pin Assignment and Package Types
2.1 Description
Die 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
Pin Number
LQFP LQFP QFN QFN 64 48 40 32 1 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Pin Name V33 DP DM VBAT PE4 PE5 PE6 PE7 NC NC PF0 PF1 PF2 PF3 PF4 PB7/AD7 PB6/AD6 PB5/AD5 PB4/AD4 PB3/AD3 PB2/AD2 PB1/AD1 PB0/AD0 SCL SDA PC0/AD8 PC1/AD9 PC2/AD10 PC3/AD11 PC4/AD12 PC5/AD13 PC6/AD14 PC7/AD15 PD0/AD16 PD1/AD17 PD2/AD18 PD3 / ADVREF
Pin Type P I/O I/O P I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Pin Description
3.3V regulator output
USB plus data line of USB upstream port. An internal 1.5KΨ ≥ 5% pull-up resistor is connected between this lead and V33 to select full-speed USB operation. The internal 1.5 KΨ resistor is controlled by DPEN. USB minus data line of USB upstream port. Power input (< 3.6V) for CPU and functions
3.3V GPIO Port, 30KΨ pull-up resistor in input mode. High Current Source/Sink Output
3.3 V GPIO Port, 30KΨ pull-up resistor in input mode. Programmable CMOS or N-ch Open Drain Output
Option 1: 3.3V GPIO Port, 30KΨ programmable pull-up resistor in input mode.
Option 2: Input of AD converter.
Clock for ISP & ICE Data for ISP & ICE
Option 1: 3.3V GPIO Port, 30KΨ pull-up resistor in input mode.
Option 2: Input of AD converter.
Option 1: 3.3V GPIO Port, 30KΨ programmable pull-up
resistor in input mode.
Option 2: Input of AD converter.
Option 1: 3.3V GPIO Port, 30KΨ programmable pull-up
resistor in input mode.
Option 2: Reference voltage Input of AD converter.
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Die 36
Pin Name
Pin Type I/O
Data Sheet Rev. 1.31
Pin Number
LQFP LQFP QFN QFN 64 48 40 32 38
31
26
18
Pin Description
Option 1: 3.3V GPIO Port, 30KΨ programmable pull-up
resistor in input mode.
Option 2: MISO for SPI
Option 1: 3.3V GPIO Port, 30KΨ programmable pull-up
resistor in input mode.
Option 2: MOSI for SPI
Option1: 3.3V GPIO Port, 30KΨ programmable pull-up
resistor in input mode
Option2: SCK for SPI
Option1: 3.3V GPIO Port, 30KΨ programmable pull-up
resistor in input mode
Option2: SSN for SPI
PD4/MISO
37 39 32 27 19 PD5/MOSI I/O
38 40 33 28 20 PD6/SCK I/O
39 40 41 42 43 44 45 46 47 48
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
34 35 36 37 38 39 40
29 30 31 32
21 22 23 24 25
PD7/SSN NC NC NC
PA0/EXINT0 PA1/EXINT1 PA2/EXINT2 PA3/EXINT3 PA4/EXINT4 PA5/EXINT5 PA6/EXINT6 PA7/EXINT7
NC NC NC PE0/PWM0
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
3.3V GPIO Port, 30KΨ pull-up resistor in input mode. High Current Source/Sink Output
49 57 41 33 PE1/PWM1 I/O
50 58 42 34 26 PE2/RX I/O
51 52 53 54 55 56 57
59 60 60 61 62 63 64
43 44 44 45 46 47 48
35 36 36 37 38 39 40
27 28 28 29 30 31 32
PE3/TX VSS VSS OSCI OSCO RESETN VDD5V
I/O P P I O I P
Option1: 3.3V GPIO Port, 30KΨ pull-up resistor in input
mode. High Current Source/Sink Output
Option2: PWM0
Option1: 3.3V GPIO Port, 30KΨ pull-up resistor in input
mode. High Current Source/Sink Output
Option2: PWM1
Option1: 3.3V GPIO Port, 30KΨ pull-up resistor in input
mode. High Current Source/Sink Output
Option2: RS232 RX
Option1: 3.3V GPIO Port, 30KΨ pull-up resistor in input
mode. High Current Source/Sink Output
Option2: RS232 TX Ground Ground
Crystal oscillator input Crystal oscillator output. System reset, low-reset 5V supply voltage input
2
Note: 6 pins (VDD5V, VSS, OSCI, RESETN, SCL, SDA pins) are used for IC-type ISP function; VBAT
pin could be short to V33 or be connected to VDD5V through diodes in the meantime.
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Data Sheet Rev. 1.31
2.2 Package Pin Configuration
(1) LQFP64-type (10mm x 10mm x 1.4mm; 7mm x 7mm x 1.4mm)
VDD5VRESETNOSCOOSCIVSSPE3/TXPE2/RXPE1/PWM1PE0/PWM0NCNCNCPA7/EXINT7PA6/EXINT6PA5/EXINT5PA4/EXINT4V33DPDMVBATPE4PE5PE6PE7NCNCPF0PF1PF2PF3PF4PB7/AD7123456789101112131415166463626160595857565554535251504948474645444342414039383736353433WT6573F - RG640/641LQFP64(10mm x 10mm / 7mm x 7mm)PA3/EXINT3PA2/EXINT2PA1/EXINT1PA0/EXINT0NCNCNCPD7/SSNPD6/SCKPD5/MOSIPD4/MISOPD3/ADVREFPD2/AD18PD1/AD17PD0/AD16PC7/AD15
(2) LQFP48-type (7mm x 7mm x 1.4mm)
VDD5VRESETNOSCOOSCIVSSPE3/TXPE2/RXPE1/PWM1PE0/PWM0PA7/EXINT7PA6/EXINT6PA5/EXINT5PB6/AD6PB5/AD5PB4/AD4PB3/AD3PB2/AD2PB1/AD1PB0/AD0SCLSDAPC0/AD8PC1/AD9PC2/AD10PC3/AD11PC4/AD12PC5/AD13PC6/AD1417181920212223242526272829303132
V33DPDMVBATPE4PF0PF1PF2PF3PF4PB7/AD7PB6/AD6123456789101112484746454443424140393837363534333231302928272625WT6573F - RG480LQFP48 (7mm x 7mm)PA4/EXINT4PA3/EXINT3PD7/SSNPD6/SCKPD5/MOSIPD4/MISOPD3/ADVREFPD2/AD18PD1/AD17PD0/AD16PC7/AD15PC6/AD14PB5/AD5PB4/AD4PB3/AD3PB2/AD2SCLSDAPC0/AD8PC1/AD9PC2/AD10PC3/AD11PC4/AD12PC5/AD13131415161718192021222324
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Data Sheet Rev. 1.31
(3) QFN40-type (6mm x 6mm x 0.75mm)
VDD5VRESETNOSCOOSCIVSSPE3/TXPE2/RXPE1/PWM1PE0/PWM0PA7/EXINT7V33DPDMVBATPF0PF1PF2PF3PF4PB5/AD51234WT6573F - UG4005QFN4067(6mm x 6mm x 0.75mm)8910111213141516171819204039383736353433323130292827262524232221PA6/EXINT6PD7/SSNPD6/SCKPD5/MOSIPD4/MISOPD3/ADVREFPD0/AD16PC7/AD15PC6/AD14PC5/AD13PB4/AD4PB3/AD3PB2/AD2SCLSDAPC0/AD8PC1/AD9PC2/AD10PC3/AD11PC4/AD12
(4) QFN32-type (5mm x 5mm x 0.75mm)
VDD5VRESETNOSCOOSCIVSSPE3/TXPE2/RXPA7/EXINT7V33DPDMVBATPE4PE5PE6PE71242233WT6573F - UG32022421QFN325(5mm x 5mm x 0.75mm)206197188179101112131415163231302928272625PA2/EXINT2PA1/EXINT1PA0/EXINT0PD7/SSNPD6/SCKPD5/MOSIPD4/MISOPD3/ADVREFWeltrend Semiconductor, Inc. U00_07_442
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PB5/AD5PB4/AD4PB3/AD3PB2/AD2PB1/AD1PB0/AD0SCLSDAWT6573F
Data Sheet Rev. 1.31
2.3 Package Outline Dimension
(1) LQFP64: 10mm x 10mm x 1.4mm
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Data Sheet Rev. 1.31
(2) LQFP64: 7mm x 7mm x 1.4mm
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Data Sheet Rev. 1.31
(3) LQFP48: 7mm x 7mm x 1.4mm
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Data Sheet Rev. 1.31
(4) QFN40: 6mm x 6mm x 0.75mm
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Data Sheet Rev. 1.31
(5) QFN32: 5mm x 5mm x 0.75mm
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PA7/EXINT7PA6/EXINT6PA5/EXINT5PA4/EXINT4PE1/PWM1PE0/PWM0RESETN
Data Sheet Rev. 1.31
2.4 Pad Diagram and Location Table
VDD5VVSSV33DPDMVBATPE4PE5PE6PE7PF0PF1PF2PF3PF4PB7/AD7WELTRENDWT6573FVSSPE2/RXPE3/TXOSCOOSCIPA3/EXINT3PA2/EXINT2PA1/EXINT1PA0/EXINT0PD7/SSNPD6/SCKPD5/MOSIPD4/MISOPD3/AVDREFPD2/AD18PD1/AD17PD0/AD16PC7/AD15PC6/AD14PB6/AD6PB5/AD5PB4/AD4PB3/AD3PB2/AD2PB1/AD1PB0/AD0SDAPC0/AD8PC1/AD9PC2/AD10PC3/AD11PC4/AD12PC5/AD13SCL
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No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Name V33 DP DM VBAT PE4 PE5 PE6 PE7 PF0 PF1 PF2 PF3 PF4 PB7/AD7 PB6/AD6 PB5/AD5 PB4/AD4 PB3/AD3 PB2/AD2 PB1/AD1 PB0/AD0 SCL SDA PC0/AD8 PC1/AD9 PC2/AD10 PC3/AD11 PC4/AD12 PC5/AD13
X 44 44 44 44 44 44 44 44 44 44 44 44 44 44 336 458 579 700 821 942 1064 1185 1306 2007 2128 2249 2371 2492 2613
Y 2125 1937 1805 1672 1551 1430 1309 1187 1066 945 824 703 581 335 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44
No 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
Name PC6/AD14 PC7/AD15 PD0/AD16 PD1/AD17 PD2/AD18 PD3 /ADVREF PD4/MISO PD5/MOSI PD6/SCK PD7/SSN PA0/EXINT0 PA1/EXINT1 PA2/EXINT2 PA3/EXINT3 PA4/EXINT4 PA5/EXINT5 PA6/EXINT6 PA7/EXINT7 PE0/PWM0 PE1/PWM1 PE2/RX PE3/TX VSS VSS OSCI OSCO RESETN VDD5V
X 2906 2906 2906 2906 2906 2906 2906 2906 2906 2906 2906 2906 2906 2906 2613 2491 2370 2249 2128 2007 1885 1764 1643 1522 933 785 660 356
Y 335 457 578 952 1073 1194 1316 1437 1558 1679 1800 1922 2043 2164 2456 2456 2456 2456 2456 2456 2456 2456 2456 2456 2456 2456 2456 2456
Data Sheet Rev. 1.31
Note 1: The origin of pad location shown here is at lower-left corner of chip and is without border street Note 2: Dice size without border street is 2950um x 2500um; the pad window is 83um x 83um. Note 3: The substrate of dice should be connected to VSS.
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Data Sheet Rev. 1.31
3. Functional Description
3.1 USB Module
The USB function interface manages communications between the Host and the USB function. The WT6573F interface consists of the USB full/low speed transceiver, the serial bus engine (SIE), the system interface logic (SIL), and the transmit / receive FIFOs. The USB transceiver in WT6573F provides a physical interface to USB lines. The SIE handles communication protocol of USB. The SIL handles data transfers and provides the interface among the SIE, the Turbo 8052 CPU and the function FIFOs.
The main blocks in the USB module are:
1. Full Speed USB Transceiver: This is an on-chip transceiver having one differential driver to
transmit the USB data onto the USB bus and single ended receivers on the D+ and D- lines as well as a differential receiver to receive the USB data signal on the USB bus.
2. Serial Bus Interface Engine (SIE): The SIE does all the front-end functions of USB protocol such
as clock/data separation, sync-field identification, NRZI-NRZ conversion, token packet decoding, bit stripping, bit stuffing, NRZ-NRZI conversion, CRC5 checking and CRC16 generation and checking. Besides, it manages detecting of reset, suspend and resume signals on the upstream port of the WT6573F to wakeup the system from the suspend state. It also provides serial-to-parallel conversion for the serial packet from the full speed USB transceiver to 8 bit parallel data to the system interface logic and for 8 bit parallel data from the system interface logic to serial packet to the full speed USB transceiver.
3. System Interface Logic (SIL): The SIL operates in conjunction with the CPU to provide the
capabilities of controlling the operation of the FIFOs. The SIL also monitors the status of the data transactions, transfers event control to the CPU through interrupt requests at the appropriate moment, initiate resume signaling to USB bus while the WT6573F is in power-down mode. Operation of the SIL is controlled through the use of external function registers.
4. Device Function: The WT6573F device function interface has eight endpoints that can support
three types of USB data transfer: control, interrupt and bulk transfer. Transmit FIFOs are written by CPU, and then read by SIL for transmission. Receive FIFO is written by the SIL following reception, and then read by the CPU. Endpoint 0 supports control transfer for configuration / command / status type communication flows between client software and function. Endpoint 1~3 supports interrupt/bulk transfer.
3.2 Micro-controller
The 8052 CPU is a high performance 8-bit on-chip micro-controller running the firmware associated with the operation of the function. It features 16K-byte Flash ROM, 512-byte RAM and three 16-bit timers. In addition, the 8052 has two power saving modes enabling further power reduction.
1. 16-bit Timer: The WT6573F has three timers that can be clocked by oscillator. It can be
programmed for applications such as periodically generating interrupt requests and serving as a firmware watchdog timer.
2. 8052 On-Chip Memory: The 8052 provides on-chip program memory beginning at location 0000H
where, following chip reset, the first instruction is fetched and executed from. The 8052 CPU also provides on-chip data RAM beginning at location 00H. Locations 00H-7FH can be accessed with direct, indirect addressing while locations 80H-FFH can only be accessed with indirect addressing. Locations 20H-2FH are bit addressable.
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3.3 Address Space Mapping
The WT6573F has six address spaces: a program memory space, an internal data memory space, an on-chip external data memory space, a special function register space (SFR), an external function register space (XFR), and a register file. Table 2 shows the addressing mapping of the WT6573F.
Memory Type Size Location Data Addressing
Indirect addressing using
Program Memory 16K bytes 0000H-3FFFH
MOVC instruction
On Chip External Data Indirect addressing using
256 Bytes 0080H-017FH
Memory MOVX instruction
XFRs (Specific Function Indirect addressing using
128 bytes 0000H-007FH
Register) MOVX instruction Internal Data Memory 128 bytes 00H-7FH Direct, Indirect addressing Internal Data Memory 128 bytes 80H-FFH Indirect addressing
8052 SFRs 128 bytes 80H-FFH Direct addressing Register File 8 bytes R0-R7 Register
Table 2. Addressing Mapping
UC0001F Memory Map Program Memory Indirect Addressing 3FFF
Data Sheet Rev. 1.31
Data Memory 017F Indirect Addressing Flash ROM External RAM Direct Addressing 00FF 0080 007F 0000 Indirect Addressing SFR Internal RAM 0080 007F 0000 Internal RAM XFR 0000
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Data Sheet Rev. 1.31
3.3.1 SPECIAL FUNCTION REGISTER ADDRESS SPACE
The special function registers (SFRs) reside in this optimized 8052 micro-controller core. Table 3 lists the location of all the WT6573F SFRs. Please refer to the 8052 data sheet for bit definition of each SFR.
Description Data Address Register Name
80H P0 Port 0 81H SP Stack Point 82H DPL Data Point Low 83H DPH Data Point High 87H PCON Power Control Register 88H TCON Timer Control Register 89H TMOD Timer Mode Register 8AH TL0 Timer 0 Low Order 8CH TH0 Timer 0 High Order 90H P1 Port 1 99H SBUF Serial Buffer 9DH SPI_CON SPI control register 9EH SPI_STA SPI Status register 9FH SPI_RX, SPI_TX SPI data register A0H P2 Port 2 A8H IE Interrupt Enable Register B0H B8H IP Interrupt Priority Register BAH BBH BCH BDH C0H XICON External interrupt control C8H T2CON Timer 2 control CAH RCAP2L T2 Capture Low CBH RCAP2H T2 Capture High CCH TL2 T2 reg. High CDH TH2 T2 reg. Low D0H PSW Program Status Word E0H ACC Accumulator F0H B B Register
Table 3. WT6573F Special Function Register Layout
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Data Sheet Rev. 1.31
3.3.2 EXTERNAL FUNCTION REGISTER ADDRESS SPACE
The 8052 is connected to one of these registers when the register is addressed by the contents of registers R0 or R1 in the internal data memory. Two instructions, MOVX @Rr, A and MOVX A, @Rr can be used for data movement between the XFRs and accumulator of the 8052. Table 8, 9 (page 21, 22) lists the location of all the XFRs. When the instruction, MOVX @Rr, A or MOVX A, @Rr, is executed, the address contained in R0 or R1 registers is latched by ALE signal and then the direction of data movement between the XFRs and the 8052 can be controlled by the signals subsequently generated by the 8052.
Please see Chapter 4. External Function Registers (XFR, page 21~22) for reference.
WR or RD
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Data Sheet Rev. 1.31
3.4 Clock Unit
The WT6573F can use an external clock or an on-chip oscillator with crystal or ceramic resonator as its clock source. The timing waveform at OSCI can be provided by:
an on-chip oscillator employing an external crystal / resonator connected across OSCI and OSCO an external clock source connected to OSCI
The frequency of clock is 12MHz or 24MHz (selectable by PLL_DIV bit in PLL_CTL XFR 3Dh) in normal operation, and is used as the internal X4/X2 PLL input, then the PLL output 48MHz clock for USB block and 24MHz clock for CPU.
As shown in Figure 1, the clock to CPU control section is stopped where \"1\" is set in bit 0 (IDL) of the power control register (PCON) in firmware, thereby the CPU operation is halted in idle mode. Idle mode freezes the clocks to the CPU at known states while the peripherals continue to be clocked. The CPU status before entering idle mode is preserved. The contents of the SFRs, XFRs and RAM are also retained. Idle mode can be used while the device is in un-enumerated state following chip reset. Activation of an enabled interrupt and a logic-high on chip reset are the ways to exit the idle mode.
The clock to where the CPU controlled section and peripherals that including some portions of USB function is stopped at where bit 1 (PD) of the power control register (PCON) is set in firmware. Therefore both oscillator and CPU operation are halted in power-down mode. The CPU status before entering power-down mode is preserved. In addition, the contents of the SFRs, XFRs and RAM are also retained. For suspend, firmware must put the WT6573F into power-down mode to meet the USB limitation of 500 οA. Activation of an enabled interrupt and a logic high on chip reset are the ways to exit the power-down mode. On Chip Peripherals OSCI CPU Freq.=12 MHz OSCO PCON [1] PCON [0] (Idle Mode) (Power Down Mode) USB_CLOCK Micro-controller Figure 1. Clock Circuit
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Data Sheet Rev. 1.31
3.5 Reset
Chip reset can be initiated by the built-in power on reset or an USB-initiated reset, or a low level of signal on the RESETN pin for at least 100us while the oscillator is running. Built-in power on reset circuit can generate a pulse to reset the entire chip.
3.6 Power-down Mode and Idle Mode
The instruction that sets PCON.0 is the last instruction executed before the idle mode is activated. Once in the idle mode the CPU status is preserved in its entirety. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware and then the idle mode is terminated.
The instruction that sets PCON.1 is the last executed prior to entering power-down mode. Once in the power-down mode, the oscillator is stopped. The contents of the on-chip RAM, the Special Function Registers and USB External Function Registers are saved. Hardware reset and activation of any enabled interrupt is the ways of exiting the power-down mode. Power-down mode should be used for USB suspend operation. PCON.1 has to be set in the ISR of interrupt caused by active SUSPEND signal.
The WT6573F can initiate resume signaling to the USB host through remote wakeup of the USB function while it is in power-down mode. While in power-down mode, remote wakeup has to be initiated through assertion of an enabled interrupt. In the ISR for the interrupt activated by active SUSPEND signal, the interrupt should be enabled in firmware prior to entering power-down mode which can be terminated by activation of an enabled interrupt signal or an enabled USB resume interrupt signal (RESUME). In the ISR, interrupt signal should be disable before escaping from power-down mode. Upon completion of the ISR, program execution continues with the instruction immediately following the instruction that activated the power-down.
Note: Add two “NOP” instructions after set power-down instruction in F/W to avoid code execution error.
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3.7 Interrupt Table
Below is the interrupt table of WT6573F:
Interrupt Factors
Internal Internal external external Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal
Reset (from RESETN pin, Watchdog Timer Reset, USB Reset)
ADC Interrupt (USBFI2.2) External Interrupt (USBFI2.3)
USB Remote Wake Up Interrupt (USBFI2.4) USB Suspend Interrupt (USBFI2.5) USB Resume Interrupt (USBFI2.6) Time-Base Interrupt (USBFI2.7) Timer 0 Interrupt (TF0)
USB Endpoint 0 Transmit Interrupt (USBFI.0) USB Endpoint 0 Receive Interrupt (USBFI.1)
USB Endpoint 1 Transmit /Receive Interrupt (USBFI.2) USB Endpoint 2 Transmit /Receive Interrupt (USBFI.3) USB Endpoint 3 Transmit /Receive Interrupt (USBFI.4) USB Reset Interrupt (USBFI.5) Timer 1 Interrupt (TF1) UART Received Interrupt (RI) UART Transmitted Interrupt (TI) Timer 2 Interrupt (TF2) SPI Interrupt (SPIF)
EA=1, IE.3=1 EA=1, IE.4=1 EA=1, IE.5=1 EA=1, XICON.6=1
001BH 0023H 002BH 0043H
5 6 7 8
EA=1, IE.2=1
0013H
4
EA=1, IE.1=1
000BH
3
EA=1, IE.0=1
0003H
2
Enable Condition Non-maskable
Vector Address 0000H
Priority Highest 1
3.8 Function Endpoint
The WT6573F supports 4 device function endpoints. Endpoint 0 contains two FIFOs for transmit and receive, respectively. Endpoint 1 to 3 can be programmed to transmit or receive. Endpoint 0 handles control data transfer. Endpoint 1 to 3 can be interrupt or bulk transfer. The EPINDEX register selects the endpoint for any given data transaction. For specific operation, the endpoint 3 can also be programmed to be used as endpoint 1 or 2 output token, and then there will be 1 transmitted and received packet in the same endpoint.
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3.9 Transmit FIFOs
3.9.1 TRANSMIT FIFOS FEATURES
The USB transmit FIFOs are data buffers with the following features (See Figure 2):
USB support for one data set of not greater than 8/16/32/64 bytes (programmable by counter setting).
a byte count register to store the number of bytes in the data set protection against overwriting data in a full FIFO capable to retransmit the current data set
7
6
5
4 3 2 Write-Pointer
Read-Pointer 1
0
Figure 2. Transmit FIFO Outline (example for 8 bytes FIFO)
The CPU writes to the FIFO location specified by the write-pointer also used as the byte-counter to indicate how many bytes have been written and not yet read by the SIL or the VFD transmitter. The write-pointer automatically increments by one after a write, and it decrements by one after a read. The read-pointer points the next FIFO location to be read by the USB SIL or the VFD transmitter. The read-pointer automatically increments by one after a read. The transmit FIFO is inhibited to be read by the SIL or the VFD transmitter when it is empty or before a data set has been successfully written into it.
3.9.2 TRANSMIT DATA SET MANAGEMENT
TXFULL = 1 in the TXFLG register, indicates data set has been written into the FIFO and is ready for transmission. Following reset, TXFULL = 0 and TXEMP = 1, signifying an empty FIFO. Only the first eight bytes of the data set which size is greater than eight are written into the FIFO. In this case, TXFULL is not set until a write to TXCNT. In the case of TXFULL = 1 farther writing to TXDAT or TXCNT are ignored. Please note that the content of TXCNT determines the number of bytes transmitted over the USB lines. Discrepancy between the byte number written to TXCNT and number of bytes actually written to the FIFO will cause an unexpected result. Read the FIFO is prohibited when the FIFO is empty or TXFULL = 0.
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Two events cause the TXFULL to be updated:
A new data set is written to the FIFO: The CPU writes bytes to the FIFO via TXDAT and writes the
number of bytes to TXCNT. TXFULL is only set after the write to TXCNT. Set TXCNT=0 indicates a zero length transmission. In this case, TXFULL is set and TXEMP remains unchanged to indicate the FIFO is still empty. This process is illustrated in Table 4.
A data set in the FIFO is successfully transmitted: The SIL reads the data set from the FIFO for
transmission. When a good transmission is acknowledged, the TXFULL is cleared and TXEMP is set.
TX TX TX Zero Length Write bytes to Data Set TX
EMP FULL EMP Transmission TXDATx Written FULL
0 0 No Yes 1 0 0 1 No Yes 1 0 0 1 Yes Write byte count to No 1 1 1 - - TXCNTx Write Ignored 1 -
Table 4. Writing to the Byte Count Register
When a good transmission is completed, both read pointer and write pointer is advanced to the start point of the FIFO to set up for transmitting the next data set. When a bad transmission is encountered, the read pointer is reversed to the start point of the FIFO to enable the SIL to re-read the last data set for retransmission. The pointer reversal and advance are accomplished automatically by hardware. Table 5 summarizes how actions following a transmission depend on TXERR and TXACK.
TXERR TXACK Action at End of Transfer Cycle 0 0 No operation 0 1 Read Pointer and Write Pointer both are set to the start point of FIFO 1 0 Read Pointer is set to the start point of FIFO
Table 5. Truth Table for Transmit FIFO Management
3.9.3 TRANSMIT FIFO REGISTERS
TXDAT, the transmit FIFO data register (see Table 17) TXCON, the transmit FIFO control register (see Table 18) TXFLG, the transmit FIFO flag register (see Table 19)
TXCNT, the transmit FIFO byte count register (see Table 20)
These registers are endpoint indexed. They are used as a set to control the operation of the transmit FIFO, associated with the current endpoint specified by the EPINDEX register
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3.10 Receive FIFOs
3.10.1 RECEIVE FIFO FEATURES
The receive FIFO is a data buffer with the following features (see Figure 3):
support for one data set of not greater than 8/16/32/64 bytes
a byte count register accesses the number of bytes in the data set flag to signal a full FIFO and an empty FIFO capability to re-receive the last data set Write-Pointer 7
6
5
4 3
2 Read-Pointer 1
0
Figure 3. Receive FIFO Outline (example for 8 bytes FIFO)
The SIL writes to the FIFO location specified by the write pointer also used as the byte-counter to indicate how many bytes have been written and not yet read by the CPU. The write-pointer automatically increments by one after a write and decrements by one after a read. The read-pointer points the next FIFO location to be read by the CPU. The read-pointer automatically increments by one after a read. The receive FIFO is inhibited to be read by the CPU when it is empty or before a data set has been successfully written into it. When a SETUP token is detected by the SIL, the SIL flushes the FIFO even if the FIFO is being read by the CPU.
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3.10.2 RECEIVE DATA SET MANAGEMENT
RXFULL = 1 in the RXFLG register, indicates the data set has been written into the FIFO and is ready for reception. Following reset, RXFULL = 0 and RXEMP = 1, signifying an empty FIFO. Only the first eight bytes of the data set which size is greater than eight are written into FIFO. RXFULL is however not set until reception is done and successfully acknowledged. RXFULL is cleared by setting the FFRC bit of RXCON in firmware to indicate the data set has successfully read by CPU. In the case of RXFULL = 1 farther writes to FIFO are ignored. Please note that the content of RXCNT should be read by CPU to determine the numbers of bytes need to be read from FIFO by CPU. Further reading from an empty FIFO is ignored.
RXFULL RXEMP Status
0 0 Data set is being written to FIFO 0 1 Empty 1 0 Data set already written to FIFO 1 1 Zero length packet received
Table 6. Status of the Receive FIFO Data Set
When a good reception is completed and the data set has been successfully read by CPU, firmware must set the FFRC bit of RXCON to advance the write pointer and read pointer to the start point of the FIFO to set up for receiving the next data set. When a bad reception is completed, the write pointer can be reversed to the position of the start point of the FIFO to enable the SIL to re-write the last data set for re-reception. The pointer advance and reversal are accomplished automatically by hardware. Table summarizes how actions following a reception depend on RXERR and RXACK.
RXERR RXACK Action at End of Transfer Cycle
0 0 No operation 0 1 Read Pointer and Write Pointer are set to the start point of
FIFO when firmware sets the FFRC bit of RXCON
1 0 Write Pointer is set to the start point of FIFO
Table 7. Truth Table for Receive FIFO Management
3.10.3 RECEIVE FIFO REGISTERS
RXDAT, the receive FIFO data register (see Table 26) RXCON, the receive FIFO control register (see Table 27) RXFLG, the receive FIFO flag register (see Table 28)
RXCNT, the receive FIFO byte count register (see Table 29)
These registers are endpoint indexed. They are used as a set to control the operation of the receive FIFO associated with the current endpoint specified by the EPINDEX register.
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3.11 Setup Token Receive FIFO Handling
SETUP tokens received by the endpoint zero must be acknowledged, even if the receive FIFO is not empty. When a SETUP token is detected by the SIL, the SIL flushes the FIFO and sets the STOVW bit of RXSTAT for reset and locking the read pointer. These prevent RXURF bit of RXFLG and the read pointer from being set if the receive FIFO flush occurs in the middle of a CPU data read cycle. The STOVW bit is cleared and the EDOVW bit is set when a SETUP packet has been successfully acknowledged. The read pointer will remain locked until both the STOVW and EDOVW bits are cleared. For SETUP packets only, firmware must clear EDOVW before reading data from the FIFO. If this is not done, data read from the FIFO will be invalid. After processing a SETUP packet, firmware should always check the STOVW and EDOVW flags before setting the RXFFRC bit. When a SETUP packet either has been or is being received, setting of RXFFRC has no effect if either STOVW or EDOVW is set.
3.12 Suspend and Resume
In order to reduce the power consumption, WT6573F automatically enters the suspend state when it has observed no bus traffic for 3 ms. When in suspend, the CPU and its peripherals are in power down mode, an interrupt is enabled to support remote wakeup. The entire chip consumes less than 500 οA in suspend-state.
WT6573F exits suspend mode when there is bus activity. A USB device may also request the host exits from suspend or selective suspend by using electrical signaling to indicate remote wakeup. The ability of a device to signal remote wakeup is optional. WT6573F allows the host to enable or disable this capability. Device states are described in Figure 4.
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Data Sheet Rev. 1.31
Reset Un-enumerated
Device
Configured
End of Interrupt Idle/Application code ≠ Device function
Transmit USB Transmit Interrupt
End of Interrupt End of Interrupt
End of Interrupt
USB Receive Setup, Interrupt Receive Resume ≠ Device interrupt disabled. USB Suspend Interrupt ≠ Power-down mode terminated
Suspend ≠Device interrupts enabled ≠WT6573F is in power- USB Resume Interrupt down mode Device Remote Wake up: ≠Device is disabled. ≠Notify SIE of remote wake-up detected Device Interrupt ≠Power-down mode terminated (remote wake-up)
Figure 4. Suspend and Resume State Diagram
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4. External Function Registers (XFR)
4.1 USB
Data Address
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH
Table 8. USB External Function Register Layout
Register Name FADDR USBFI USBFIE SIEI
EPINDEX EPCON WDTRST TXDAT TXCON TXFLG TXCNT TXSTAT
USBFI2 USBFIE2 EPREP TXEN
RXDAT RXCON RXFLG RXCNT RXSTAT
Description
Function Address Register
USB Function Interrupt Register
USB Function Interrupt Enable Register SIE Interface Register
Endpoint Index Register
Endpoint Data-flow Control Register Watchdog Timer Reset Register Transmit USB FIFO Data Register Transmit USB FIFO Control Register Transmit USB FIFO Flag Register
Transmit USB FIFO Byte Count Register Endpoint Transmit Status Register
USB Function Interrupt Register 2
USB Function Interrupt Enable Register 2 Endpoint Replace Register
Transmit Receive Enable Flag Register
Receive FIFO Data Register Receive FIFO Control Register Receive FIFO Flag Register
Receive FIFO Byte Count Register Endpoint Receive Status Register
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4.2 Interrupt, Watch-dog, PWM, Ports, ADC XFR Definition
Data Address
1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 3DH 3EH
Table 9. Interrupt/Watch-dog/Ports/ADC External Function Register Layout
Register Name PA PD PE PF
EXINTEN WDTEXT RMPEN PWM0 PWM1 PWM_CTL ADL ADH ADC
PUPCTRLB PUPCTRLD ADCHENR1 ADCHENR2 ADCHENR3 PAOE PDOE PEOE PFOE TBCR PFOD PLL_CTL INT3
Description
Port A (corresponding to P0) data Port D data Port E data Port F data
Enable/Disable Control for External Interrupts Extension of watch-dog timer
Enable/Disable port Remote wakeup PWM0 Duty Setting PWM1 Duty Setting Control of PWM AD data lower 8 bits AD data upper 4 bits AD Control bits
PB Programmable Pull-up PD Programmable Pull-up
ADC Channel Enable Select, bit 7:0 ADC Channel Enable Select, bit 15:8 ADC Channel Enable Select, bit 18:16 PA Output Enable PD Output Enable PE Output Enable PF Output Enable
Time Base Control Register PF Open-drain Output PLL control register Interrupt 3 source
Data Sheet Rev. 1.31
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5. Register Descriptions
5.1 USB Related Registers
Address: 00H FADDR
Reset State: x000 0000B
Function Address Register. This XFR holds the address for the USB function. During bus enumeration, it is written with a unique value assigned by the host. Reset state is by USB reset or hardware reset.
7 0 --- FA6:0
Bit Function Bit
Number Mnemonic
7 --- Reserved:
7-bit Programmable Function Address:
This register is programmed through the commands received via
6:0 FA6:0 endpoint 0 on configuration, which should be the only time the firmware
should change the value of this register. This register is hardware read-only.
Table 10. Function Address Register
Address: 01H USBFI
Reset State: xx00 0000B
USB Function Interrupt Register. A ‘1’ indicates that an interrupt (INT1 of 8052 CPU) is actively pending. All bits are cleared after a read. Reset state is by hardware reset.
7 0
USBRT USBx USBx USBx USBRx USBTx
--- ---
INT 3INT 2INT 1INT 0INT 0INT
Bit Function Bit
Mnemonic Number
7:6 --- Reserved 5 USBRTINT USB reset interrupt 4 USBx3INT Function Transmit/Receive Done Flag for endpoint 3 3 USBx2INT Function Transmit/Receive Done Flag for endpoint 2 2 USBx1INT Function Transmit/Receive Done Flag for endpoint 1 1 USBRx0INT Function Receive Done Flag for endpoint 0 0 USBTx0INT Function Transmit Done Flag for endpoint 0
Table 11. USB Function Interrupt Register
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Address: 02H USBFIE
Reset State: 0000 0000B
USB Function Interrupt Enable Register. Reset state is by hardware reset.
7 0
USBRT USBx USBx USBx USBRx USBTx
--- ---
_IE 3INT_IE 2INT_IE 1INT_IE 0INT_IE 0INT_IE
Bit Bit
Function
Mnemonic Number
7:6 --- Reserved 5 USBRT_IE USB reset interrupt enable
Function Transmit/Receive Done Interrupt Enable 3:
4 USBx3INT_IE Enable function transmit/receive done interrupt for endpoint 3
(USBx3INT).
Function Transmit/Receive Done Interrupt Enable 2:
3 USBx2INT_IE Enable function transmit/receive done interrupt for endpoint 2
(USBx2INT).
Function Transmit/Receive Done Interrupt Enable 1:
2 USBx1INT_IE Enable function transmit/receive done interrupt for endpoint 1
(USBx1INT).
Function Transmit Receive Done Interrupt Enable 0:
1 USBRx0INT_IE Enable function transmit receive done interrupt for endpoint 0
(USBRx0INT).
Function Transmit Done Interrupt Enable 0:
0 USBTx0INT_IE Enable function transmit done interrupt for endpoint 0
(USBTx0INT).
Table 12. USB Function Interrupt Enable Register
For all bits, a ‘1’ means the interrupt is enabled and will cause an interrupt to be signaled to the micro-controller. A ‘0’ means the associated interrupt source is disabled and cannot cause an interrupt.
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Address: 03H SIEI
Reset State: 0x10 x000B
USB SIE Interface Register.
Bit 7, bit5~4 and bit2~1 are reset by hardware reset only, Bit0 is reset by USB reset or hardware reset.
7 0 FSEN USBRSTV33EN DM --- USBRSTEN DP WAKEUP
_LONG
Bit Bit
Function
Number Mnemonic
Full Speed Enable. When active ‘1’, indicates that the SIE is running in full speed mode. When active ‘0’, indicates that the SIE is running in
7 FSEN low speed mode. The signal should not change outside the
SYS_RESET window and should be stable for at least one USB_CLK cycle before the assertion of SYS_RESET. USB reset flag (read only).
USBRST_LWhen active ’1’, indicates that USB reset appears. When active ’0’,
6
ONG indicates that USB reset disappear. USBRST_LONG active later than
SE0.
5 V33EN Regulator Enable, 1: enable, 0: disable
DM Pull-up Enable:
When this bit is cleared, DM transceiver pad will not provide 3.3V output and is in high impedance state. In this case, the 1.5KΨ resistor
4 DM
does not connect to the DM line and the upstream port of the device is disconnected. Set this bit for normal operation. This bit is not reset by USB reset.
3 --- Reserved
USB Reset Enable:
2 USBRSTEN Set this bit to enable USB reset. This bit should be set at least 500οs
after DPEN is set. This bit is not reset by USB reset. DP Pull-up Enable:
When this bit is cleared, DP transceiver pad will not provide 3.3V output and is in high impedance state. In this case, the 1.5KΨ resistor
1 DP
does not connect to the DP line and the upstream port of the device is disconnected. Set this bit for normal operation. This bit is not reset by USB reset. Wakeup:
This bit is used by the USB function to initiate a remote wakeup. Set by
0 WAKEUP
firmware to drive resume signaling on the USB lines to the host or upstream hub. Cleared by hardware when resume signaling is done.
Table 13. USB SIE Interface Register
Note:
When FSEN = 1 (enable Full-speed function), system clock is 24MHz;
When FSEN = 0 (disable Full-speed function), the frequency of system clock is a quarter of the
external crystal oscillator. For example, if a 12MHz crystal oscillator is connected between OSCI and OSCO pins, the system clock would be 3MHz.
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Address: 05H EPINDEX
Reset State: xxxx xx00B
Endpoint Index Register. This Register identifies the endpoint pair. Its contents select the transmit and receive FIFO pair and serve as an index to endpoint-specific XFRs. Reset state is by USB reset or hardware reset.
7 0 --- --- --- --- --- --- EPINX1 EPINX0
Bit Bit
Function
Mnemonic Number
7:2 --- Reserved
Endpoint Index: 00 = Endpoint 0.
1:0 EPINX1:0 01 = Endpoint 1.
10 = Endpoint 2. 11 = Endpoint 3.
Table 14. Endpoint Index Register
The value in this register selects the associated bank of endpoint-indexed XFRs including TXDAT, TXCON, TXFLG, TXCNT, TXSTAT, RXDAT, RXCON, RXFLG, RXCNT, RXSTAT, EPCON, EPREP.
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Address: 06H EPCON
001x 0101B (Endpoint-indexed) Reset State: Endpoint 0
Function Endpoint 1,2,3 00xx 0000B
Endpoint Control Register. This XFR configures the operation of the endpoint specified by EPINDEX. Reset state is by USB reset or hardware reset.
7 0 RXSTL TXSTL CTLEP --- RXIE RXEPEN TXOE TXEPEN
Bit Bit
Function
Mnemonic Number
Stall Receive Endpoint:
Set this bit to stall the receive endpoint. Clear this bit only when the host has intervened through commands sent down endpoint 0. When this bit is set and RXSETUP is clear, the receive endpoint will
7 RXSTL
respond with a STALL handshake to a valid OUT token. When this bit is set and RXSETUP is set, the receive endpoint will NAK. This bit does not affect the reception of SETUP token by a control endpoint.
Stall Transmit Endpoint:
Set this bit to stall the transmit endpoint. This bit should be cleared only when the host has intervened through commands sent down
6 TXSTL endpoint 0. When this bit is set and RXSETUP is clear, the receive
endpoint will respond with a STALL handshake to a valid IN token. When this bit is set and RXSETUP is set, the receive endpoint will NAK.
Control Endpoint:
5 CTLEP Set this bit to configure the endpoint as a control endpoint. Only
control endpoint is capable of receiving SETUP tokens.
4 --- Reserved:
Receive Input Enable:
Set this bit to enable data from the USB to be written into the receive FIFO. If cleared, the endpoint will not write the received data into the receive FIFO and at the end of reception, but will return a
3 RXIE
NAK handshake on a valid OUT token if the RXSTL bit is not set. This bit does not affect a valid SETUP token. A valid SETUP token and packet overrides this bit if it is cleared, and place the receive data in the FIFO.
Receive Endpoint Enable:
Set this bit to enable the receive endpoint. When disabled, the
2 RXEPEN endpoint does not respond to valid OUT or SETUP token. This bit is
hardware read-only and has the highest priority among RXIE and RXSTL. Note that endpoint 0 is enabled for reception upon reset. Transmit Output Enable:
This bit is used to enable the data in TXDAT to be transmitted. If
1 TXOE
cleared, the endpoint returns a NAK handshake to a valid IN token if the TXSTL bit is not set. Transmit Endpoint Enable:
This bit is used to enable the transmit endpoint. When disabled, the
0 TXEPEN endpoint does not response to a valid IN token. This bit is hardware
read-only. Note that endpoint 0 is enabled for transmission upon reset.
Table 15. Endpoint Control Register
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Address: 07H WDTRST
Reset State: xxxx xxxxB
Watchdog Timer Reset Register. After device reset, the hardware watchdog is cleared and disabled. Write AAH to WDTRST register can clear and enable the watchdog timer. The watchdog timer overflows in 10.9 ms. If the WDT overflows, it initiates a device reset. Firmware should write AAH to WDTRST to clear the WDT before it overflows.
7 0
WDTRST7:0
Bit Bit
Function
Mnemonic Number
Watchdog Timer Reset (write-only):
7:0 WDTRST7:0
Write AAH to clear and enable the WDT.
Table 16. Watchdog Timer Reset Register
Address: 08H TXDAT
(Endpoint-indexed) Reset State: xxxx xxxx B
Transmit FIFO Data Register. Data to be transmitted by the FIFO specified by EPINDEX is first written to this register.
7 0
TXDAT7:0
Bit Bit
Function
Mnemonic Number
Transmit Data Byte (write-only):
7:0 TXDAT7:0 To write data to the transmit FIFO, write to this register. The write
pointer is incremented automatically after a write.
Table 17. Transmit FIFO Data Register
Address: 09H TXCON
(Endpoint-indexed) Reset State: 0xxx xxxxB
Transmit FIFO Control Register. Controls the transmit FIFO specified by EPINDEX. Reset state is by the hardware reset.
7 0 TXCLR --- --- --- --- --- --- ---
Bit Bit
Function
Mnemonic Number
Transmit Clear:
Setting this bit flushes the transmit FIFO, resets all the read/write
7 TXCLR
pointers, sets the EMPTY bit in TXFLG, and clears all other bits in TXFLG. After the flush, hardware clears this bit.
6:0 --- Reserved
Table 18. Transmit FIFO Control Register
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Address: 0AH TXFLG
(Endpoint-indexed) Reset State: xxxx 1000B
Transmit FIFO Flag Register. These flags indicate the status of data packets in the transmit FIFO specified by EPINDEX. Reset state is by the hardware state.
7 0 --- --- --- --- TXEMP TXFULL TXURF TXOVF
Bit Bit
Function
Mnemonic Number
Reserved:
7:4 --- Values read from these bits are indeterminate. Write zeros to these
bits.
Transmit FIFO Empty Flag (read-only):
Hardware sets this bit when the data set has been read out of the transmit FIFO by SIL. Hardware clears this bit when the empty
3 TXEMP
condition no longer exists. This bit always tracks the current transmit FIFO status. This flag is also set when a zero-length data packet is transmitted.
Transmit FIFO Full Flag (read-only):
This flag indicates the data set is present in the transmit FIFO. This
2 TXFULL bit is set after write to TXCNT to reflect the condition of the data set.
Hardware clears this bit when the data set has been successfully transmitted.
Transmit FIFO Under-run Flag (read-, clear-only)*:
Hardware sets this flag when an addition byte is read from an empty transmit FIFO. This is a sticky bit that must be cleared through
1 TXURF
firmware by writing a ‘0’ to this bit. When the transmit FIFO under-runs, the read pointer will not advance – it remains locked in the empty position.
Transmit FIFO Overrun Flag (read-, clear-only)*:
This bit is set when an additional byte is written to a FIFO with TXFULL = 1. This is a sticky bit that must be cleared through
0 TXOVF
firmware by writing a ‘0’ to this bit. When the transmit FIFO overruns, the write pointer will not advance – it remains locked in the full position.
Table 19. Transmit FIFO Flag Register
* When set, all transmissions are NAKed.
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Address: 0BH TXCNT
(Endpoint-indexed) Reset State: X000 0000B
Transmit FIFO Byte Count Register. This register stores the number of bytes for the data packet in the transmit FIFO specified by EPINDEX. Reset state is by the hardware reset.
7 0 --- TXCNT6:0
Bit Bit
Function
Mnemonic Number
7 --- Reserved
Transmit Byte Count (write-only):
The number of bytes in the data set written to the transmit FIFO.
6:0 TXCNT[6:0]
When this register is written, TXFULL is set. Write the byte count to this register after writing data set to TXDAT.
Table 20. Transmit FIFO Byte Count Register
To send a status stage after a control write or no data control command or a null packet, write 0 to TXCNT.
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Address: 0CH TXSTAT
(Endpoint-indexed) Reset State: 0xxx x000B
Endpoint Transmit Status Register. Contains the current endpoint status of the transmit FIFO specified by EPINDEX. Reset state is by the hardware reset.
7 0 TXSEQ --- --- --- --- TXVOID TXERR TXACK
Bit Bit
Function
Mnemonic Number
Transmit Current Sequence Bit (read, clear-only):
This bit will be transmitted in the next PID and toggled on a valid
7 TXSEQ ACK handshake. This bit is toggled by hardware on a valid SETUP
token. The SIE will handle all sequence bit tracking. This bit should only be used when initializing a new configuration or interface. Reserved:
6:3 ---
Write zeros to these bits. Transmit Void (read-only):
A void condition has occurred in response to a valid IN token. Transmit void is closely associated with the NAK/STALL handshake returned by the function after a valid IN token, due to the conditions
2 TXVOID that cause the transmit FIFO to be unable or not ready to transmit.
Use this bit to check any NAK/STALL handshake returned by the function. This bit does not affect the USBTxxINT, TXERR or TXACK bit. This bit is updated by hardware at the end of a non-isochronous transaction in response to a valid IN token. Transmit Error (read-only):
An error condition has occurred with the transmission. Complete or partial data has been transmitted. The error can be one of the following:
1 TXERR 1. Data transmitted successfully but no handshake received.
2. Transmit FIFO goes into under-run condition while transmitting. The corresponding transmit done bit is set when active. This bit is updated by hardware along with the TXACK bit at the end of data transmission (this bit is mutually exclusive with TXACK). Transmit Acknowledge (read-only):
Data transmission completed and acknowledged successfully. The
0 TXACK corresponding transmit done bit is set when active. This bit is
updated by hardware along with the TXERR bit at the end of data transmission (this bit is mutually exclusive with TXERR).
Table 21. Endpoint Transmit Status Register
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WT6573F
Address: 11H USBFI2
Reset State: 0000 11xxB
USB Function Interrupt Register 2. Contains USB suspend and USB resume. A ‘1’ indicates that an interrupt (INT0 of 8052 CPU) is actively pending. Users should write a value ‘0’ to clear register bit. Bit6 to bit4 is reset by USB reset or hardware reset. Bit7 is reset by hardware reset only
7 0 TBIF RESUME SUSPEND RMPINT --- --- EXINT ADINT
Bit Bit
Function
Mnemonic Number
7 TBIF Time base interrupt
USB SIE has detected a RESUME signaling on the USB lines. This
6 RESUME
interrupt is used to terminate the power-down mode.
USB SIE has detected a SUSPEND signaling on the USB lines. The
5 SUSPEND corresponding ISR should put the whole chip into power-down
mode.
(Remote wake up interrupt enable) During suspend, if any of the
4 RMPINT enabled port (see RMPEN) detects “low”, then RMPINT is set and
remote-wakeup is processed
3 EXINT External Interrupt flag
AD Converter Interrupt flag. This bit is set when the AD conversion
2 ADINT
is completed.
1 --- Reserved 0 --- Reserved
Table 22. USB Function Interrupt Register 2
Data Sheet Rev. 1.31
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Data Sheet Rev. 1.31
Address: 12H USBFIE2
Reset State: 0000 0x00B
USB Function Interrupt Enable Register 2. Reset state is by hardware reset.
7 0 NAKINT RESUMESUSPENSTALLINTGERR_IADINT_I
--- ---
_IE _IE D_IE T_IE E E
Bit Bit
Function
Mnemonic Number
NAK Interrupt Enable:
7 NAKINT_IE Set this bit to enable USB interrupt for hub and function even if NAK
or STALL handshake is returned.
6 RESUME_IE RESUME Interrupt Enable.
SUSPEND
5 SUSPEND Interrupt Enable.
_IE
STALL Interrupt Enable:
4 STALLINT_IE Set this bit to enable USB interrupt for hub and function if STALL
handshake is returned.
RX-TOGGLE-ERROR Interrupt Enable:
3 TGERR_IE Set this bit to enable USB interrupt for hub and function if data
toggle mismatch is found (RX_ERR/RXACK is cleared)
2 ADINT_IE ADINT Interrupt Enable 1:0 --- Reserved
Table 23. USB Function Interrupt Enable Register 2
For all bits, a ‘1’ means the interrupt is enabled and will cause an interrupt to be signaled to the micro-controller. A ‘0’ means the associated interrupt source is disabled and cannot cause an interrupt.
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Data Sheet Rev. 1.31
Address: 13H EPREP
Reset State: xxxx xx00B
Endpoint Replace register. This XFR is only valid while EPINDEX = 5 ~ 7. Reset state is by USB reset or hardware reset.
7 0
EPREP 1:0
Bit Bit
Function
Mnemonic Number
7:2 --
0: No FIFO is replaced
1: FIFO3 acts as Transmit FIFO of endpoint 1
1:0 EPREP[1:0]
2: FIFO3 acts as Transmit FIFO of endpoint 2 3: Reserved
Table 24. Endpoint Replace Register
Address: 14H TXEN
Reset State: xxxx xxx0B
Transmit Receive Enable Flag Register
7 0
--- --- --- --- --- --- TXEN ---
Bit Bit
Function
Mnemonic Number
7:1 --
Read only.
0 TXEN TXEN=0, SETUP or OUT token.
TXEN=1, IN token
Table 25. Transmit Receive Enable Flag Register
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Data Sheet Rev. 1.31
Address: 18H RXDAT
(Endpoint-indexed) Reset State: xxxx xxxxB
Receive FIFO Data Register. Receive FIFO data specified by EPINDEX is stored and read from this register.
7 0
RXDAT7:0
Bit Bit
Function
Mnemonic Number
Receive Data Byte (read-only):
To write data to the receive FIFO, the SIL writes to this register. To
7:0 RXDAT7:0 read data from the receive FIFO, the CPU reads from this register.
The write pointer and read pointer are incremented automatically after a write and read, respectively.
Table 26. Receive FIFO Data Register
Address: 19H RXCON
(Endpoint-indexed) Reset State: 0xx0 xxxxB
Receive FIFO Control Register. Controls the receive FIFO specified by EPINDEX. Reset state is by USB reset or hardware reset.
7 0 RXCLR --- --- RXFFRC --- --- --- ---
Bit Bit
Function
Mnemonic Number
Clear the Receive FIFO:
Set this bit to flush the entire receive FIFO. All flags in RXFLG
7 RXCLR
revert to their reset states (RXEMP is set; all other flags clear). Hardware clears this bit when the flush operation is complete.
6:5 --- Reserved
FIFO Read Complete:
Set this bit to release the receive FIFO when a data set read is complete. Setting this bit clears the RXFULL bit (in the RXFLG
4 RXFFRC register) corresponding to the data set that was just read. Hardware
clears this bit after the RXFULL bit is cleared. All data from this data set must have been read. Note that FIFO Read Complete only works if STOVW and EDOVW are cleared.
3:0 --- Reserved
Table 27. Receive FIFO Control Register
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Data Sheet Rev. 1.31
Address: 1AH RXFLG
(Endpoint-indexed) Reset State: 000x 1000B
Receive FIFO Flag Register. These flags indicate the status of data packets in the Receive FIFO specified by EPINDEX. Reset state is by USB reset or hardware reset.
7 0 SENDNASENDSTTGERR --- RXEMP RXFULL RXURF RXOVF
K ALL
Bit Bit
Function
Mnemonic Number
NAK flag (read-, clear-only):
7 SENDNAK This flag indicates a NAK is returned to host while NAKINT_IE is
set.
STALL flag (read-, clear-only):
6 SENDSTALL This flag indicates a STALL is returned to host while STALLINT_IE
is set.
RX-TGERR flag (read-, clear-only):
5 TGERR
This flag indicates data toggle error is found while TGERR_IE is set.
4 --- Reserved
Receive FIFO Empty Flag (read-only):
Hardware sets this bit when the data set has been read out of the
3 RXEMP receive FIFO. Hardware clears this bit when the empty condition no
longer exists. This is not a sticky bit and always tracks the current status. This flag is also set when a zero-length packet is received. Receive FIFO Full Flag (read-only):
This flag indicates the data set is present in the receive FIFO. Hardware sets this bit when the data set has been successfully
2 RXFULL
received. This bit is cleared after write to RXCNT to reflect the condition of the data set. Likewise, this bit is cleared after setting of the RXFFRC bit.
Receive FIFO Under-run Flag (read-, clear-only)*:
Hardware sets this bit when an additional byte is read from an
1 RXURF empty receive FIFO. This bit is cleared through firmware by writing a
‘0’ to this bit. When the receive FIFO under-runs, the read pointer will not advance -- it remains locked in the empty position. Receive FIFO Overrun Flag (read-, clear-only)*:
This bit is set when the SIL writes an additional byte to a receive FIFO with RXFULL = 1. This is a sticky bit that must be cleared
0 RXOVF through firmware by writing a ‘0’ to this bit, although it can be
cleared by hardware if a SETUP packet is received after an RXOVF error had already occurred. When the receive FIFO overruns, the write pointer will not advance -- it remains locked in the full position.
Table 28. Receive FIFO Flag Register
* When set, all transmissions are NAKed.
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Data Sheet Rev. 1.31
Address: 1BH RXCNT
(Endpoint-indexed) Reset State: X000 0000B
Receive FIFO Byte Count Register. This register is used to store the number of byte for the data packed received in the receive FIFO specified by EPINDEX. Reset state is by USB reset or hardware reset.
7 0 --- RXCNT6:0
Bit Bit
Function
Mnemonic Number
Reserved:
7 ---
Always zeros.
Byte Count (read-only):
The number of bytes in data set written to the receive FIFO. When this register is written, RXFULL is not set until reception is
6:0 RXCNT[6:0] successfully acknowledged. After the SIL writes a data set to the
RXFIFO, it writes the byte count to this register. The CPU reads the byte count from this register to determine how many bytes to read from the RXFIFO.
Table 29. Receive FIFO Byte Count Register
Address: 1CH RXSTAT
(Endpoint-indexed) Reset State: 0000 0000B
Endpoint Receive Status Register. Contains the current endpoint status of the receive FIFO specified by EPINDEX. Reset state is by USB reset or hardware reset.
7 0
--- RXVOID RXERR RXACK RXSEQ RXSETUSTOVW EDOVW
P
Bit Bit
Function
Number Mnemonic
Receive Endpoint Sequence Bit (read, clear-only):
This bit will be toggled on completion of an ACK handshake in response to an OUT token. This bit will be set (or created) by hardware after reception of
7 RXSEQ
SETUP token. The SIE will handle all sequence bit tracking. This bit should only be used when initializing a new configuration or interface. If you don’t want to change sequence bit, set this bit to ‘1’ when you write this register. Receive Setup Token (read-, clear-only):
This bit is set by hardware when a valid SETUP token has been received. When SIL set this bit, it causes received IN or OUT token to be NAKed until the bit is cleared to allow a control transaction. IN or OUT token is
6 RXSETUP
NAKed even if the endpoint is stalled (RXSTL or TXSTL) to allow a control transaction to clear a stalled endpoint. Clear this bit upon detection of a SETUP token after the firmware is ready to complete the setup stage of control transaction.
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Bit Number
Bit Mnemonic
Function
Start Overwrite Flag (read-only):
Set by hardware upon receipt of SETUP token for any control endpoint to indicate that the receive FIFO is being overwritten with new SETUP data. When set, the FIFO state (RXFULL and read pointer) resets and is locked for this endpoint until EDOVW is set. This prevents a prior, ongoing firmware read from corrupting the read pointer as the receive FIFO is being cleared and new data is being written into it. This bit is cleared by hardware at the end of handshake phase transmission of the setup stage. This bit is used only for control endpoint.
End Overwrite Flag (read-, clear-only):
This flag is set by hardware during the handshake phase of a SETUP stage. It is set after every SETUP packet is received and must be cleared prior to reading the contents of the FIFO. When set, the FIFO state (RXFULL and read pointer) remains locked for this endpoint until this bit is cleared. This prevents a prior, ongoing firmware read from corrupting the read pointer after the new data has been written into the receive FIFO. This bit is only used for control endpoint.
Note: Make sure the EDOVW bit is cleared prior to reading the contents of the receive FIFO. Reserved:
Write zero to this bit.
Receive Void Condition (read-only):
This bit is set when no valid data is received in response to a SETUP or OUT token due to one of the following conditions: 1. The receive FIFO is still locked.
2. The EPCON register’s RXSTL bit is set.
This bit is set and cleared by hardware. This bit is updated by hardware at the end of the transaction in response to a valid OUT token. Receive Error (read-only):
Set when an error condition has occurred with the reception. Complete or partial data has been written into the receive FIFO. No handshake is returned. The error can be one of the following conditions: 1. Data failed CRC check. 2. Bit stuffing error.
3. A receive FIFO goes into overrun or under-run condition while receiving. This bit is updated by hardware at the end of a valid SETUP or OUT token transaction. The corresponding receive done bit is set when active. This bit is updated with the RXACK bit at the end of data reception and is mutually exclusive with RXACK.
Receive Acknowledged (read-only):
This bit is set when data is received completely into a receive FIFO and an ACK handshake is sent. This read-only bit is updated by hardware at the end of valid SETUP or OUT token transaction. The corresponding receive done bit set when active. This bit is updated with the RXERR bit at the end of data reception and is mutually exclusive with RXERR. Table 30. Endpoint Receive Status Register
Data Sheet Rev. 1.31
5 STOVW
4 EDOVW
3 ---
2 RXVOID
1 RXERR
0 RXACK
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5.2 Interrupt, Watch-dog, PWM, Ports, ADC Registers
Address: PA
Reset State: PA read/write data. Reset state by hardware reset. 7 PA7 PA6 PA5 PA4 PA3 PA2
Bit Bit
Function
Number Mnemonic 7:0 PA PA data
Table 31. PA Register
Address: PD
Reset State:
PD read/write data 7 PD7 PD6 PD5 PD4 PD3 PD2
Bit Bit
Function
Number Mnemonic 7:0 PD PD data
Table 32. PD Register
Address: PE
Reset State:
PE read/write data 7 PE7 PE6 PE5 PE4 PE3 PE2
Bit Bit
Function
Number Mnemonic 7:0 PE PE data
Table 33. PE Register
1DH
0000 0000B PA1
0 PA0
Data Sheet Rev. 1.31
1EH
0000 0000B PD1
0 PD0
1FH
0000 0000B PE1
0 PE0
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Data Sheet Rev. 1.31
Address: PF
Reset State:
PF read/write data 7 --- --- --- PF4 PF3 PF2 Bit Bit
Function
Number Mnemonic 7:5 --- Reserved 4:0 PF[4:0] PF data
Table 34. PF Register
Address: EXINTEN
Reset State:
External interrupt enable from PA. 7
EXINTEN7
EXINTEN6
EXINTEN5
EXINTEN4
EXINTEN3
20H
XXX0 0000B PF1
0 PF0
21H
xxxx xxx0B
EXINTEN1
0
EXINTEN0
EXINTEN2
Bit Bit
Number Mnemonic 7:0 EXINTEN[7:0]
Function
Enable external interrupt of port A
Table 35. External Interrupt Enable Register
Address: WDTEXT
Reset State:
Extension of the Watch-Dog Timer. Reset state is by hardware reset. 7
---
---
WDTEXT5
WDTEXT4
WDTEXT3
WDTEXT2
22H
xx00 0000B
WDTEXT1
0
WDTEXT0
Bit
Number 7:6 5:0
Bit
Mnemonic ---
WDTEXT[5:0]
Function
Reserved
111111:Extend the watchdog timer by 63 times 111110:Extend the watchdog timer by 62 times |
000011:Extend the watchdog timer by 3 times 000010:Extend the watchdog timer by 2 times 000001:Extend the watchdog timer by 1 times 000000: No watchdog timer extension. Table 36. Watch-dog Timer Extension Register
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Data Sheet Rev. 1.31
Address: 23H RMPEN
Reset State: xx00 0000B
Port Remote wakeup Enable Control. Reset state is by hardware state. 7 0 --- --- RMPENF RMPENE RMPEND RMPENC RMPENB RMPENA
Bit Bit
Function
Number Mnemonic 7:6 --- Reserved
Port F Remote-wakeup Enable
5 RMPENF 1: Enable
0: Disable
Port E Remote-wakeup Enable
4 RMPENE 1: Enable
0: Disable
Port D Remote-wakeup Enable
3 RMPEND 1: Enable
0: Disable
Port C Remote-wakeup Enable
2 RMPENC 1: Enable
0: Disable
Port B Remote-wakeup Enable
1 RMPENB 1: Enable
0: Disable
Port A Remote-wakeup Enable
0 RMPENA 1: Enable
0: Disable
Table 37. Port Remote Wakeup Enable Register
Address: 24H PWM0
Reset State: 0000 0000B
PWM0 Duty Control 7 0
PWM0[7] PWM0[6] PWM0[5] PWM0[4] PWM0[3] PWM0[2] PWM0[1] PWM0[0]
Bit Bit
Function
Number Mnemonic
0000 0000: Duty cycle = 0 (all low level) 0000 0001: Duty cycle = 1/256 0000 0010: Duty cycle = 2/256 0000 0011: Duty cycle = 3/256
7:0 PWM0[7:0]
1111 1101: Duty cycle = 253/256 1111 1110: Duty cycle = 254/256 1111 1111: Duty cycle = 255/256
Table 38. PWM0 Duty Control Register
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Data Sheet Rev. 1.31
Address: 25H PWM1
Reset State: 0000 0000B
PWM1 Duty Control 7 0
PWM1[7] PWM1[6] PWM1[5] PWM1[4] PWM1[3] PWM1[2] PWM1[1] PWM1[0] Bit Bit
Function
Number Mnemonic
0000 0000: Duty cycle = 0 (all low level) 0000 0001: Duty cycle = 1/256 0000 0010: Duty cycle = 2/256 0000 0011: Duty cycle = 3/256
7:0 PWM1[7:0] :
:
1111 1101: Duty cycle = 253/256 1111 1110: Duty cycle = 254/256 1111 1111: Duty cycle = 255/256
Table 39. PWM1 Duty Control Register
Address: 28H PWM_CTL
Reset State: 0000 0000B
PWM0/PWM1 Control 7 0
FSEL[3:0] Reserved PWMEN1 PWMEN0
Bit Bit
Function
Number Mnemonic
PWM Base Clock / Frequency Selection:
0000: Base clock = 8MHz, PWM frequency = 31.25KHz 0001: Base clock = 4MHz, PWM frequency = 15.625KHz 0010: Base clock = 2MHz, PWM frequency = 7.8125KHz 0011: Base clock = 1MHz, PWM frequency = 3.906KHz 0100: Base clock = 500KHz, PWM frequency = 1.593KHz 0101: Base clock = 250KHz, PWM frequency = 976.6Hz 0110: Base clock = 125KHz, PWM frequency = 488.3Hz 0111: Base clock = 62.5KHz, PWM frequency = 244.1Hz 1000: Base clock = 31.25KHz, PWM frequency = 122Hz
7:4 FSEL[3:0]
1001: Base clock = 15.625KHz, PWM frequency = 61Hz 1010: Base clock = 7.8125KHz, PWM frequency = 30.5Hz 1011: Reserved 1100: Reserved
1101: Base clock = Timer0 Output,
PWM frequency = Timer0 Output Frequency / 256
1110: Base clock = Timer1 Output,
PWM frequency = Timer1 Output Frequency / 256 1111: Base clock = Timer2 Output,
PWM frequency = Timer2 Output Frequency / 256
3:2 --- Reserved 1 PWMEN1 1: PWM1 Enable; 0: Disable 0 PWMEN0 1: PWM0 Enable; 0: Disable
Note: When PWMEN1 (PWMEN0) is set, the corresponding bit from PEOE [1:0] is ignored and PE1 (PE0) is set to output always.
Table 40. PWM0/PWM1 Control Register
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ADL
ADC Lower Byte Data 7 ADB7 ADB6 Bit Bit
Number Mnemonic 7:0 ADB[7:0]
ADH
ADC Upper Byte Data 7 --- ---
Bit Bit
Number Mnemonic 7:4 --- 3:0 ADB[11:8]
Address: Reset State:
ADB5
ADB4
ADB3
ADB2
Data Sheet Rev. 1.31
29H
0000 0000B
ADB1
0
ADB0
Function
ADC Lower Data Byte
Address: Reset State:
---
---
Function
Reserved
ADC Higher Data Byte
Table 41. ADC Lower and Upper Byte Data Register
ADB11
ADB10
2AH
XXXX 0000B
ADB9
0
ADB8
Address: 2BH ADC
Reset State: 0000 000XB
ADC Control Register 7 0 ADON ADEN ADSEL[4] ADSEL[3] ADSEL[2] ADSEL[1] ADSEL[0] ---
Bit Bit
Function
Number Mnemonic 7 ADON 0: Disable ADC for power-down mode
1: Turn on ADC
6 ADEN ADC Start Bit
Every time want to start an A/D function, set ADEN. After A/D function finished (A/D interrupt), ADEN is reset by hardware.
5:1 ADSEL[4:0] 00000: Select AD0 input pin
00001: Select AD1 input pin 00010: Select AD2 input pin 00011: Select AD3 input pin 00100: Select AD4 input pin 00101: Select AD5 input pin |
10010: Select AD18 input pin Others: Invalid
0 --- Reserved
Table 42. ADC Control Register
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Data Sheet Rev. 1.31
Address: 2CH PUPCTRLB
Reset State: 1111 1111B
PB Pull-up Resistor Control Register 0: Disable 1: Enable 7 0 PUAD7 PUAD6 PUAD5 PUAD4 PUAD3 PUAD2 PUAD1 PUAD0
Bit Bit
Function
Number Mnemonic 7 PUAD7 Pin PB7/AD7 pull-up resistor control 6 PUAD6 Pin PB6/AD6 pull-up resistor control 5 PUAD5 Pin PB5/AD5 pull-up resistor control 4 PUAD4 Pin PB4/AD4 pull-up resistor control 3 PUAD3 Pin PB3/AD3 pull-up resistor control 2 PUAD2 Pin PB2/AD2 pull-up resistor control 1 PUAD1 Pin PB1/AD1 pull-up resistor control 0 PUAD0 Pin PB0/AD0 pull-up resistor control
Table 43. PB Pull-up Resistor Control Register
Address: 2DH PUPCTRLD
Reset State: 1111 1111B
PD Pull-up Resistor Control Register 0: Disable 1: Enable 7 0 PUPD7 PUPD6 PUPD5 PUPD4 PUPD3 PUAD18 PUAD17 PUAD16
Bit Bit
Function
Number Mnemonic 7 PUPD7 Pin PD7/SSN pull-up resistor control 6 PUPD6 Pin PD6/SCK pull-up resistor control 5 PUPD5 Pin PD5/MOSI pull-up resistor control 4 PUPD4 Pin PD4/MISO pull-up resistor control 3 PUPD3 Pin PD3/ADVref pull-up resistor control 2 PUAD18 Pin PD2/AD18 pull-up resistor control 1 PUAD17 Pin PD1/AD17 pull-up resistor control 0 PUAD16 Pin PD0/AD16 pull-up resistor control
Table 44. PD Pull-up Resistor Control Register
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Address: Reset State:
Data Sheet Rev. 1.31
ADCHENR1
AD channel Enable/Disable 0: Disable 1: Enable 7
ADCHEN7
ADCHEN6
ADCHEN5
2EH
0000 0000B
ADCHEN2
ADCHEN1
0
ADCHEN0
ADCHEN4 ADCHEN3
Bit
Number 7 6 5 4 3 2 1 0
Bit
Mnemonic ADCHEN7 ADCHEN6 ADCHEN5 ADCHEN4 ADCHEN3 ADCHEN2 ADCHEN1 ADCHEN0
Function
Enable/Disable AD channel 7 Enable/Disable AD channel 6 Enable/Disable AD channel 5 Enable/Disable AD channel 4 Enable/Disable AD channel 3 Enable/Disable AD channel 2 Enable/Disable AD channel 1 Enable/Disable AD channel 0
Table 45. ADC Channel Selection Register 1
When an ADCHENR1 bit is enabled, the corresponding bit from PBOE (7:0) is ignored and the corresponding pin from PB (7:0) is set the input mode always.
Address: 2FH ADCHENR2
Reset State: 0000 0000B
AD channel Enable/Disable 0: Disable 1: Enable 7 0
ADCHEN15
ADCHEN14
ADCHEN13
ADCHEN12 ADCHEN11
ADCHEN10
ADCHEN9
ADCHEN8
Bit
Number 7 6 5 4 3 2 1 0
Bit
Mnemonic ADCHEN15 ADCHEN14 ADCHEN13 ADCHEN12 ADCHEN11 ADCHEN10 ADCHEN9 ADCHEN8
Function
Enable/Disable AD channel 15 Enable/Disable AD channel 14 Enable/Disable AD channel 13 Enable/Disable AD channel 12 Enable/Disable AD channel 11 Enable/Disable AD channel 10 Enable/Disable AD channel 9 Enable/Disable AD channel 8
Table 46. ADC Channel Selection Register 2
When an ADCHENR2 bit is enabled, the corresponding bit from PCOE (7:0) is ignored and the corresponding pin from PC (7:0) is set the input mode always.
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Address: Reset State:
Data Sheet Rev. 1.31
ADCHENR3
AD channel Enable/Disable 0: Disable 1: Enable 7
---
---
---
30H
xxxx 0000B
---
ADVREF
ADCHEN18
ADCHEN17
0
ADCHEN16
Bit
Number 7 6 5 4 3 2 1 0
Bit
Mnemonic --- --- --- ---
ADVREF ADCHEN18 ADCHEN17 ADCHEN16
Function
Reserved Reserved Reserved Reserved
Enable ADVref function
Enable/Disable AD channel 17 Enable/Disable AD channel 16 Enable/Disable AD channel 15
Table 47. ADC Channel Selection Register 3
When an ADCHENR3 bit is enabled, the corresponding bit from PDOE (3:0) is ignored and the corresponding pin from PD (3:0) is set the input mode always.
Since VREF voltage for ADC should come from external source, please make sure to set ADVREF bit to 1 while using ADC function.
Address: 31H PAOE
Reset State: 0000 0000B
PA Output Enable 0: Disable 1: Enable 7 0 PAOE7 PAOE6 PAOE5 PAOE4 PAOE3 PAOE2 PAOE1 PAOE0
Bit Bit
Function
Number Mnemonic 7:0 PAOE[7:0] PA Output Enable 7:0
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PDOE
PD Output Enable 0: Disable 1: Enable 7 PDOE7 PDOE6
Bit Bit
Number Mnemonic 7:0 PDOE[7:0]
PEOE
PE Output Enable 0: Disable 1: Enable 7 PEOE7 PEOE6
Bit Bit
Number Mnemonic 7:0 PEOE[7:0]
PFOE
PF Output Enable 0: Disable 1: Enable 7 --- ---
Bit Bit
Number Mnemonic 7:5 --- 4:0 PFOE[4:0]
Address: Reset State:
Data Sheet Rev. 1.31
32H
0000 0000B
PDOE5
PDOE4
PDOE3
PDOE2
PDOE1 0
PDOE0
Function
PD Output Enable 7:0
Address: Reset State:
33H
0000 0000B
PEOE5
PEOE4
PEOE3
PEOE2
PEOE1 0
PEOE0
Function
PE Output Enable 7:0
Address: Reset State: 34H
XXX0 0000B
---
PFOE4
Function
PFOE3
PFOE2
PFOE1 0
PFOE0
Reserved
PF Output Enable 4:0
Table 48. PA, PD, PE, PF Output Enable Registers
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Data Sheet Rev. 1.31
Address: 35H TBCR
Reset State: X000 0000B
Time Base Control Register 7 0 --- TBR[2] TBR[1] TBR[0] TBACK TBIE TBON TBEN
Bit Bit
Function
Number Mnemonic
7 --- Reserved 6:4 TBR[2:0] Interrupt period time = 2^(8-TBR[2:0])*1024/32000 (sec) 3 TBACK Set to 1 to clear the time-base interrupt 2 TBIE Time-base interrupt enable 1 TBON Enable the time-base clock 0 TBEN Set to 1 to enable the 32kHz ring oscillator
While using time-base timer, please set TBEN = 1 first and then set TBON = 1
Time-base Interrupt Period Time Table
TBR[2:0]
Min. (25.6kHz) Typical (32kHz) Max. (38.4kHz)
0 10.24s 8.192s 6.827s 1 5.120s 4.096s 3.413s 2 2.560s 2.048s 1.707s 3 1.280s 1.024s 853ms 4 640ms 512ms 427ms 5 320ms 256ms 213ms 6 160ms 128ms 107ms 7 80ms 64ms 53ms
Table 49. Time Base Control Register
Address: 36H PFOD
Reset State: XXX0 0000B
PF Open-Drain Output 0: CMOS Output 1: Open-drain Output 7 0 --- --- --- PFOD4 PFOD3 PFOD2 PFOD1 PFOD0
Bit Function Bit
Number Mnemonic 7:5 --- Reserved 4 PFOD4 PF Open-Drain Output 4 3 PFOD3 PF Open-Drain Output 3 2 PFOD2 PF Open-Drain Output 2 1 PFOD1 PF Open-Drain Output 1 0 PFOD0 PF Open-Drain Output 0
Table 50. Port F Open-drain Output Control Register
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Data Sheet Rev. 1.31
Address: PLL_CTL
Reset State:
PLL control register. Reset state by hardware reset. 7 --- --- --- --- --- EXTEN
Bit Bit
Function
Number Mnemonic 7:3 --- Reserved 2 EXTEN
PLL ON/OFF control
1 PLL_OFF 1: PLL is turned OFF
0: PLL is turned ON
PLL clock source selection
0 PLL_DIV 1: 24MHz
0: 12MHz
Table 51. PLL Control Register
Address: INT3
Reset State:
Interrupt 3 Register 7 --- --- --- --- --- ---
Bit Function Bit
Number Mnemonic 7:2 --- Reserved 1 SPIINT 0 --- Reserved
Table 52. Interrupt 3 Register
3DH
xxxx x000B
0
PLL_OFF PLL_DIV
3EH
xxxx xx0xB
SPIINT 0 ---
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Data Sheet Rev. 1.31
5.3 SPI SFR
Name SPI_CON SPI_STA SPI_TX SPI_RX
SFR address
0x9D 0x9E 0x9F 0x9F
W/R W/R R W R
Description
SPI control register SPI Status register Data transfer register Data Receive register
SPI_CON register
7 SPE MSTR SPTIE SPRIE CPOL CPHA SPR1
SPE: SPI bus enable. It must be set before any control register have any effect. MSTR: mode selection 1: master; 0: slave SPTIE: SPI transmit interrupt enable SPRIE: SPI receive interrupt enable
CPOL: Clock polarity; please see Figure 5~8 for details. CPHA: Clock phase; please see Figure 5~8 for details. SPR [1:0]: SPI Baud rate selection
0 : CPU clock / 12 => 2MHz for CPU clock = 24MHz; 1 : CPU clock / 24 => 1MHz for CPU clock = 24MHz; 2 : CPU clock / 48 => 500KHz for CPU clock = 24MHz; 3 : CPU clock / 96 => 250KHz for CPU clock = 24MHz;
For full speed: CPU clock=24MHz; for low speed: CPU clock= 3MHz
Write SPI DATASCK12D6D63D5D54D4D45D3D36D2D27D1D18D0D00 SPR0
DATA OUTDATA INSample in receptionD7D7
Figure 5. SPI Timing Plot (CPOL=0, CPHA=0)
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Write SPI DATASCK12D6D63D5D54D4D45D3D36D2D27D1D18D0D0
Data Sheet Rev. 1.31
DATA OUTDATA INSample in receptionD7D7Figure 6. SPI Timing Plot (CPOL=0, CPHA=1)
Write SPI DATASCK12D6D63D5D54D4D45D3D36D2D27D1D18D0D0
DATA OUTDATA INSample in receptionD7D7Figure 7. SPI Timing Plot (CPOL=1, CPHA=0)
Write SPI DATASCK12D6D63D5D54D4D45D3D36D2D27D1D18D0D0
DATA OUTDATA INSample in receptionD7D7Figure 8. SPI Timing Plot (CPOL=1, CPHA=1)
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Data Sheet Rev. 1.31
SPI_STA status register
7 0
--- --- --- --- --- FULL OVERFLOW EMPTY
FULL: indicate the receive data register full, the receive interrupt will be generated when SPRIE=1; OVERFLOW: indicate the receive data register overflow EMPTY: indicate the transmit data register empty; the transmit interrupt will be generated when
SPTIE=1;
SPI_TX register
7 0 D7 D6 D5 D4 D3 D2 D1 D0
The (D7, D6, D5, D4, D3, D2, D1, D0) data will be transmitted.
SPI_RX register
7 0 D7 D6 D5 D4 D3 D2 D1 D0
The receive data register
5.4 UART 115200/230400 Baud Rate
PCON 7 SMOD SMOD1
Bit Bit
Number Mnemonic
7 6 5 4 3 2 1 0
SMOD SMOD1 Reserved -- GF1 GF0 PD IDL
Address: Reset State:
- Function
0: Normal operation
1: Timer 1 is used to generate baud rate, and UART is in mode 1~3 0: standard UART baud rate
1: TH1 clock frequency is multiplied by 6;
For UART 115200bps baud rate, set “X6” =1 & TH1=230 = E6h For UART 230400bps baud rate, set “X6” =1 & TH1=243 = F3h Please set to “0” Reserved
Reserved for users’ versatile applications Reserved for users’ versatile applications 0: CPU & peripherals remain active 1: CPU & peripherals are halted 0: CPU remain active 1: CPU is halted
--
GF1
GF0
PD 0x87H
00x0 0000B
0 IDL
2SMOD24000000
For example, Baud Rate (115200 bps) =xx6SMOD1=, 115384bsp, is 0.16%
323x(256/TH1)
tolerance with 115200bps, where SMOD=1, SMOD1=1, TH1=230= E6h.
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Data Sheet Rev. 1.31
6. Application Circuits
6.1 Case 1: Only USB or 5V-power-supply is used:
Enable internal regulator and USB, connect 5V-power-supply or USB VBUS line to VDD5V pin, connect V33 pin to VBAT pin. Whole system (except USB and regulator) will work with 3.3V.
WT6573FVDD5VV33VBATUSB Vbus or 5V-power-supply
6.2 Case 2: Only Battery (<3.6V) is used:
Disable USB and internal regulator, let VDD5V and V33 open, connect battery voltage to VBAT pin. Whole system (except USB and regulator) will work with VBAT voltage.
WT6573FVDD5VV33VBATNCNC2.4 ~ 3.6VBattery
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Data Sheet Rev. 1.31
6.3 Case 3: Both USB and Battery are used:
Connect 5V-power-supply or USB VBUS line to VDD5V pin, connect battery voltage to VBAT pin; insert diodes between VDD5V pin and VBAT pin to make sure VBAT is not higher than 3.6V. The battery here could be chargeable or non-chargeable. One GPIO is used to detect the existence of USB (or 5V-power-supply).
Whole system (except USB and regulator) will work with VBAT voltage. WT6573FVDD5VV33VBATGPIO (Pxx)2.4 ~ 3.6VUSB Vbus or 5V-power-supplyBattery(Chargeable or non-chargeable)
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Data Sheet Rev. 1.31
7. Electrical Characteristics
7.1 Absolute Maximum Ratings
Parameter Min. Max. Units
DC Supply Voltage (VDD5V) -0.3 7.0 V DC Supply Voltage (VBAT) -0.3 4.0 V Input and output voltage with respect to Ground -0.3 VBAT + 0.3 V Storage temperature (Tstg) -25 125 Ambient temperature with power applied (Ta) -10 85
Note: The absolute maximum ratings are rated values which must not be exceeded during operation,
even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the users. Therefore, when designing products which include this device, please ensure that no absolute maximum rating value will ever be exceeded.
7.2 D.C. Characteristics
Symbol
VDD5V VBAT IDD1 IDD2 IPD VIH1 VIH2 VIL1 VIL2 VOH VOL IIL RPH V33
(VDD=5V ± 5%, GND=0V, Ta = 25″C, System clock = 24MHz, unless otherwise noted) Parameter Condition Min. Typ. Max. Units
+ 5V Supply Voltage 4.0
Supply Voltage for CPU and
2.4
functions
System Clock = 24MHz, USB is
Operating Current 1 -
enabled, VDD=5V
System Clock = 24MHz, USB is
Operating Current 2 -
disabled, VDD=VBAT=3.3V WT6573F enters power-down
Power-down Current mode, and 32kHz Oscillator is -
disabled too
0.2VBAT Input High Voltage (except
+ 0.9 RESETN, DP, DM pin)
Input High Voltage for
0.7VBAT
RESETN pin
Input Low Voltage (except
-0.3
RESETN, DP, DM pin) Input Low Voltage for
-0.3
RESETN pin
IOH = -8.6mA, VBAT=3.3V Output High Voltage IOL = 8.6mA Output Low Voltage 0V < VIN < VDD Input Leakage Current
Pull High Resistance
VDD = 5.0V, I = 50mA 3.3V Regulator Output
5 3.3 20 18 - - - 2.7
0.7 1 30 3.3
5.25 3.6 - - 1 VBAT + 0.3 VBAT + 0.3 1.2 1.6
V V mA mA µA V V V V V V µA KΩ V
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