FPGA TX Interface
Overview
The FPGA TX interface is the FPGA’s gateway to the TX datapath of the GTX transceiver. Applications transmit data through the GTX transceiver by writing data to the TXDATA port on the positive edge of TXUSRCLK2.
The width of the port can be configured to be one, two, or four bytes wide. The actual width of the port depends on the GTX_DUAL tile's INTDATAWIDTH setting (controls the width of the internal datapath), and whether or not the 8B/10B encoder is enabled. Port widths can be 8 bits, 10 bits, 16 bits, 20 bits, 32 bits, and 40 bits.
The rate of the parallel clock (TXUSRCLK2) at the interface is determined by the TX line rate, the width of the TXDATA port, and whether or not 8B/10B encoding is enabled. A second parallel clock (TXUSRCLK) must be provided for the internal PCS logic in the transmitter. This chapter shows how to drive the parallel clocks and explains the
constraints on those clocks for correct operation. The highest transmitter data rates require a 4-byte interface to achieve a TXUSRCLK2 rate in the specified operating range.
Ports and Attributes
Table6-1 defines the FPGA TX interface ports.
Table 6-1:
FPGA TX Interface PortsPort
DirectionClock Domain
Description
Specifies the width of the internal datapath for the entire GTX_DUAL tile. This shared port is also described in “Shared PMA PLL,” page 86. •0: Internal datapath is 16 bits wide•1: Internal datapath is 20 bits wide
The REFCLKOUT port from each GTX_DUAL tile provides direct access to the reference clock provided to the shared PMA PLL (CLKIN). It can be routed for use in the FPGA logic.
TXCHARDISPMODE and TXCHARDISPVAL allow control of the 8B/10B outgoing data disparity when 8B/10B encoding is enabled.
When 8B/10B encoding is disabled, TXCHARDISPMODE is used to extend the data bus for TX interfaces with a width that is a multiple of 10. See “FPGA TX Interface,” page 120.
In
TXUSRCLK2
TXCHARDISPMODE[3] corresponds to TXDATA[31:24]TXCHARDISPMODE[2] corresponds to TXDATA[23:16]TXCHARDISPMODE[1] corresponds to TXDATA[15:8]TXCHARDISPMODE[0] corresponds to TXDATA[7:0]Table6-5, page133 shows how to use TXCHARDISPMODE to control the disparity of outgoing data when 8B/10B encoding is enabled.
INTDATAWIDTHInAsync
REFCLKOUTOutN/A
TXCHARDISPMODE0[3:0]TXCHARDISPMODE1[3:0]
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UG198 (v3.0) October 30, 2009
Configurable 8B/10B Encoder
K Characters
The 8B/10B table includes special characters (K characters) that are often used for control functions. To transmit TXDATA as a K character instead of regular data, the TXCHARISK port must be driven High. If TXDATA is not a valid K character, the encoder drives TXKERR High.
Running Disparity
8B/10B uses running disparity to balance the number of ones and zeros transmitted. Whenever a character is transmitted, the encoder recalculates the running disparity. The current TX running disparity can be read from the TXCHARDISP port. This running disparity is calculated several cycles after the TXDATA is clocked into the FPGA TX interface, so it cannot be used to decide the next value to send, as required in some protocols.
Normally, running disparity is used to determine whether a positive or negative 10-bit code is transmitted next. The encoder allows the next disparity value to be controlled directly as well, to accommodate protocols that use disparity to send control information. For example, an Idle character sent with reversed disparity might be used to trigger clock correction. Table6-5 shows how the TXCHARDISPMODE and TXCHARDISPVAL ports are used to control outgoing disparity values.Table 6-5:
TXCHARDISPMODE and TXCHARDISPVAL vs. Outgoing Disparity
TXCHARDISPVAL
0101
Outgoing Disparity
Calculated normally by the 8B/10B encoderInverts normal running disparity when encoding TXDATA
Forces running disparity negative when encoding TXDATA
Forces running disparity positive when encoding TXDATA
TXCHARDISPMODE
0011
8B/10B Bypass
The encoder offers total control of outgoing data using the TXBYPASS8B10B signal. To bypass the 8B/10B encoding and write the outgoing 10-bit code directly, TXBYPASS8B10B must be driven High. When TXBYPASS8B10B is High, the TX interface for the byte is the same as in Figure6-2, page123. Bypassing the encoder using TXBYPASS8B10B does not reduce latency, but it does allow each byte of the TX interface to be bypassed individually on a cycle-by-cycle basis.
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
TX Out-of-Band/Beacon Signaling
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 6:GTX Transmitter (TX)
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Chapter 7:GTX Receiver (RX)
Ports and Attributes
Table7-27 defines the RX comma alignment and detection ports.
Table 7-27:
RX Comma Alignment and Detection PortsPort
Dir
Clock Domain
Description
This signal from the comma detection and realignment circuit is High to indicate that the parallel data stream is properly aligned on byte boundaries according to comma detection. 0: Parallel data stream not aligned to byte boundaries
RXBYTEISALIGNED0RXBYTEISALIGNED1
Out
RXUSRCLK2
1: Parallel data stream aligned to byte boundaries
There are several cycles after RXBYTEISALIGNED is asserted before aligned data is available at the FPGA RX interface.
RXBYTEISALIGNED responds to plus comma alignment when PCOMMA_ALIGN is TRUE. RXBYTEISALIGNED responds to minus comma alignment when MCOMMA_ALIGN is TRUE.This signal from the comma detection and realignment circuit indicates that the byte alignment within the serial data stream has changed due to comma detection.
Out
RXUSRCLK2
0: Byte alignment has not changed1: Byte alignment has changed
Data can be lost when alignment occurs, which can cause data errors (and disparity errors when the 8B/10B decoder is used).
This signal is asserted when the comma alignment block detects a comma. The assertion occurs several cycles before the comma is
RXUSRCLK2available at the FPGA RX interface.
0: Comma not detected
1: Comma detected
RXCOMMADETUSE activates the comma detection and alignment circuit.
RXCOMMADETUSE0RXCOMMADETUSE1
In
RXUSRCLK2
0: Bypass the circuit
1: Use the comma detection and alignment circuit
Bypassing the comma and alignment circuit reduces RX datapath latency.
RXENMCOMMAALIGN0RXENMCOMMAALIGN1
Aligns the byte boundary when comma minus is detected.
In
RXUSRCLK2
0: Disabled1: Enabled
RXBYTEREALIGN0RXBYTEREALIGN1
RXCOMMADET0RXCOMMADET1
Out
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