High speed memory system

专利名称：High speed memory system发明人：Fu-Chieh Hsu,Wingyu Leung申请号：US10329015申请日：20021223

公开号：US20030097535A1公开日：20030522

专利附图：

摘要：A method and structure for implementing a DRAM memory array as a secondlevel cache memory in a computer system. The computer system includes a centralprocessing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU,and a second level cache memory which includes a DRAM array coupled to the CPU bus.

When accessing the DRAM array, row access and column decoding operations areperformed in a self-timed asynchronous manner. Predetermined sequences of columnselect operations are then performed in a synchronous manner with respect to a clocksignal. A widened data path is provided to the DRAM array, effectively increasing the datarate of the DRAM array. By operating the DRAM array at a higher data rate than the CPUbus, additional time is provided for precharging the DRAM array. As a result, theprecharging of the DRAM array is transparent to the CPU bus. A structure and methodcontrol the refresh and internal operations of the DRAM array.

申请人：HSU FU-CHIEH,LEUNG WINGYU

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