HV100/HV101HV100HV101
Demo KitAvailable3-Pin Hotswap, Inrush Current Limiter Controllers(Negative Supply Rail)General Description
The HV100/HV101 are 3-pin hotswap controllers available inSOT-223 and MLP packages, which require no external compo-nents other than a pass element. The HV100/HV101 containmany of the features found in hotswap controllers with 8 pins ormore, and which generally require many external components.These features include undervoltage (UV) detection circuits,power on reset (POR) supervisory circuits, inrush current limit-ing, short circuit protection, and auto-retry. In addition, theHV100/HV101 use a patent pending mechanism to sample andadapt to any pass element, resulting in consistent hotswapprofiles without any programming.
The only difference between the HV100 and the HV101 is theinternally set undervoltage (UV) threshold.
Features
❑❑❑❑❑❑❑❑❑❑
33% Smaller than SOT-232
Pass Element is Only External PartNo Sense Resistor requiredAuto-Adapt* to Pass ElementShort Circuit Protection*
UV & POR Supervisory Circuits2.5s Auto Retry
±10V to ±72V Input Voltage Range
0.6mA Typical Operating Supply CurrentBuilt in Clamp for AC Path Turn On Glitch
Applications
❑❑❑❑❑❑❑❑❑❑
-48V Central Office Switching (line cards)+48V Server Networks
+48V Storage Area Networks
+48V Peripherals, Routers, Switches
+24V Cellular and Fixed Wireless (bay stations, line cards)+24V Industrial Systems+24V UPS Systems
-48V PBX & ADSL Systems (line cards)Distributed Power SystemsPowered Ethernet for VoIP
Ordering Information
UVOptions34V14VPackageOptions3-PinSOT-2233-PinMLPHV100K5HV100K6HV101K5HV101K6DieHV100XHV101XTypical Applications and Waveforms
GNDVPP400µFDC/DCConverter+5VCOMHV100GATEVNN-48VIRF530*Patents Pending1
IRF530 is a Trademark of International Rectifier Corporation2
MLP3x2 Package Version compared to 3mmx3mm SOT-23-6
08/26/02
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate \"products liabilityindemnification insurance agreement.\" Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due toworkmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to theSupertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.1
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HV100/HV101
Electrical Characteristics (-40°C < TA < +85°C unless otherwise noted)
SymbolParameterMinTypMaxUnitsConditionsSupply(ReferencedtoVPPpin)VNNINNSupplyVoltageSupplyCurrent-720.6UV1.0VmAVNN=-48VUVControl(ReferencedtoVNNpin)VUVLVUVHUVThreshold(HightoLow)UVHysteresis3012.33414313815.7VVVVHV100HV101HV100HV101GateDriveOutput(ReferencedtoVNNpin)VGATESRGATEIGATEDOWNIPULLUPMaximumGateDriveVoltageInitialSlewRateGateDrivePull-DownCurrent(sinking)PostHotSwapPull-upCurrent101.7586122.51611143.25VV/msmAµACGATE=1nFVGATE=1V;VPP=11.5VVGATE=6VTimingControl(ReferencedtoVNNpin)tPORtARDInsertionPORDelayAutoRestartDelay1.51.253.52.55.53.75mssExampleElectricalResults(UsingIRF530)ILIMILIMILIMISHORTtSHORT∆GATEtHSMaxInrushCurrentDuringHotswapMaxInrushCurrentDuringHotswapMaxInrushCurrentDuringHotswapMaxCurrentIntoaShortShortedLoadDetecTimeInitialRateofRiseofGateHotSwapPeriodtoFullGateVoltage1.42.53.14.01.02.512.5AAAAmsV/msmsIRF530externalMOSFET,CLOAD=100µFIRF530externalMOSFET,CLOAD=200µFIRF530externalMOSFET,CLOAD=300µFIRF530externalMOSFET,RLOAD=<<1IRF530externalMOSFET,RLOAD=<<1IRF530externalMOSFET,anyCLOADIRF530externalMOSFET,anyCLOADAbsolute Maximum Ratings*
VPP Input Voltage
Operating Ambient Temperature RangeOperating Junction Temperature RangeStorage Temperature Range
*All voltages referenced to VNN.
Pinouts
2 -0.3V to 75V-40°C to +85°C-40°C to 125°C-65°C to 150°C
Top ViewSOT-2231VPP2VNN3GATEPin Description
VPPVNNGATE
–Positive voltage supply input to the circuit.
–This pin is the Negative voltage power supply input tothe circuit.–This is the Gate Driver Output for the external N-Channel MOSFET.
VNN2Top View3 pin MLP1VPP3GATE2
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HV100/HV101
Functional Block Diagram
VPPRegulatorUVLOReferenceGeneratorUVPORTimerLogicRestartTimerGATEVNNFunctional Description
Insertion into Hot Backplanes
Telecom, data network and some computer applications requirethe ability to insert and remove circuit cards from systemswithout powering down the entire system. Since all circuit cardshave some filter capacitance on the power rails, which is espe-cially true in circuit cards or network terminal equipment utilizingdistributed power systems, the insertion can result in high inrushcurrents that can cause damage to connector and circuit cardsand may result in unacceptable disturbances on the systembackplane power rails.
The HV100/HV101 are designed to facilitate the insertion andremoval of these circuit cards or connection of terminal equip-ment by eliminating these inrush currents and powering up thesecircuits in a controlled manner after full connector insertion hasbeen achieved. The HV100/HV101 are intended to provide thiscontrol function on the negative supply rail.
After completion of a full POR period, the MOSFET gate Auto-Adapt operation begins. A reference current source is turned onwhich begins to charge an internal capacitor generating a rampvoltage which rises at a slew rate of 2.5 V/ms. This referenceslew rate is used by a closed loop system to generate a GATEoutput current to drive the gate of the external N-channelMOSFET with a slew rate that matches the reference slew rate.Before the gate crosses a reference voltage, which is well belowthe VTH of industry standard MOSFETs, the pull-up current valueis stored and the Auto-Adapt loop is opened. This stored pull-upcurrent value is used to drive the gate during the remainder of thehot swap period. The result is a normalization with CISS , whichfor most MOSFETs scales with CRSS.
The MOSFET gate is charged with a current source until itreaches its turn on threshold and starts to charge the loadcapacitor. At this point the onset of the Miller Effect causes theeffective capacitance looking into the gate to rise, and the currentsource charging the gate will have little effect on the gate voltage.The gate voltage remains essentially constant until the outputcapacitor is fully charged. At this point the voltage on the gate ofthe MOSFET continues to rise to a voltage level that guaranteesfull turn on of the MOSFET. It will remain in the full on state untilan input under voltage condition is detected.
If the circuit attempts turn on into a shorted load, then the MillerEffect will not occur. The gate voltage will continue to riseessentially at the same rate as the reference ramp indicating thata short circuit exists. This is detected by the control circuit andresults in turning off the MOSFET initiating a 2.5 second delay,after which a normal restart is attempted.
If at any time during the start up cycle or thereafter, the inputvoltage falls below the UV threshold the GATE output will bepulled down to VNN, turning off the N-channel MOSFET and allinternal circuitry is reset. A normal restart sequence will beinitiated once the input voltage rises above the UVLO thresholdplus hysteresis.
Description of Operation
On initial power application the high input voltage internal regu-lator seeks to provide a regulated supply for the internal circuitry.Until the proper internal voltage is achieved all circuits are heldreset by the internal UVLO and the gate to source voltage of theexternal N-channel MOSFET is held off. Once the internalregulator voltage exceeds the UVLO threshold, the inputundervoltage detection circuit (UV) senses the input voltage toconfirm that it is above the internally programmed threshold. Ifat any time the input voltage falls below the UV threshold, allinternal circuitry is reset and the GATE output is pulled down toVNN. UVLO detection works in conjunction with a power on reset(POR) timer of approximately 3.5ms to overcome contact bounce.Once the UVLO is satisfied the gate is held to VNN until a PORtimer expires. Should the UV monitor toggle before the PORtimer expires, the POR timer will be reset. This process will berepeated each time UVLO is satisfied until a full POR period hasbeen achieved.
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HV100/HV101
Application Information
Turn On Clamp
Hotswap controllers using a MOSFET as the pass element allinclude a capacitor divider from VPP to VNN through CLOAD, CRSSand CGS. In most competitive solutions a large external capacitoris added to the gate of the pass element to limit the voltage onthe gate resulting from this divider. In those instances if a gatecapacitor is not used the internal circuitry is not available to holdoff the gate and therefore a fast rising voltage input will cause thepass element to turn on for a moment. This allows current spikesto pass through the MOSFET.
The HV100/HV101 include a built-in clamp to ensure that thisspurious current glitch does not occur. The built-in clamp willwork for the time constants of most mechanical connectors.There may be applications, however, that have rise times thatare much less than 1µs (100’s of ns). In these instances it maybe necessary to add a capacitor from the MOSFET gate tosource to clamp the gate and suppress this current spike. Inthese cases the current spike generally contains very littleenergy and does not cause damage even if a capacitor is notused at the gate.
Short Circuit Protection
The HV100/HV101 provide short circuit protection by shuttingdown if the Miller Effect associated with hotswap does not occur.Specifically, if the output is shorted then the gate will rise withoutexhibiting a “flat response”. Due to the fact that we have normal-ized the hotswap period for any pass element, a timer can beused to detect if the gate voltage rises above a threshold withinthat time, indicating that a short exists. The diagram belowshows a typical turn on sequence with the load shorted, resultingin a peak current of 4A.
2A/div
Auto-Adapt Operation
The HV100/HV101 Auto-adapt mechanism provides an impor-tant function. It normalizes the hotswap period regardless ofpass element or load capacitor for consistent hotswap results.By doing this it allows the novel short circuit mechanism to workbecause the mechanism requires a known time base.
The maximum current that may occur during this period can becontrolled by adding a resistor in series with the source of theMOSFET. The lower graph shows the same circuit with a 100mΩresistor inserted between source and VNN. In this case themaximum current is 25% smaller.
The above diagram illustrates the effectiveness of the auto-adapt mechanism. In this example three MOSFETs with differentCISS and RDSON values are used. The top waveform is the hotswapcurrent, while the bottom waveform is the gate voltage. As canbe seen, the hotswap period is normalized, the initial slope of thegate voltage is approximately 2.5V/ms regardless of the MOSFET,and the total hotswap period and peak currents are a function ofa MOSFET type dependent constant multiplied by CLOAD.Typically if MOSFETs of the same type are used, the hotswapresults will be extremely consistent. If different types are usedthey will usually exhibit minimal variation.
For most applications and pass elements, the HV100/HV101provides adequate limiting of the maximum current to preventdamage without the need for any external components. The 2.5sdelay of the auto-retry circuit provides time for the pass elementto cool between attempts.
NTE66 is a trademark of NTE Electronics
IRF530 is a trademark of International Rectifier CorporationIRF120M is a trademark of International Rectifier Corporation
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HV100/HV101
Application Information, cont’d.
Auto-Retry
Not only does the HV100/HV101 provide short circuit protectionin a 3-pin package, it also includes a 2.5s built in auto-restarttimer. The HV100/HV101 will continuously try to turn on thesystem every 2.5s, providing sufficient time for the pass elementto cool down after each attempt.
Programming the HV100/HV101
The HV100/HV101 require no external components other than apass element to provide the functionality described thus far. Insome applications it may be useful to use external componentsto adjust the maximum allowable inrush current, adjust UVLO, orto provide additional gate clamping if the supply rails have risetimes below 1ms.
All of the above are possible with a minimum number of externalcomponents.i)
To adjust inrush current with an external component simplyconnect a capacitor (CFB) from drain to gate of the MOSFET.The inrush calculation then becomes:
IINRUSH = (CISS / (CRSS + CFB)) * 2.5e3 * CLOAD
Note that a resistor (approximately 10KΩ) needs to beadded in series with CFB to create a zero in the feedback loopand limit the spurious turn on which is now enhanced by thelarger divider element.ii)
To increase undervoltage lockout simply connect a Zenerdiode in series with the VPP pin.
2A/div
Calculating Inrush Current
As can be seen in the diagram below, for a standard passelement, the HV100/HV101 will normalize the hotswap timeperiod against load capacitance. For this reason the current limitwill increase with increasing value of the load capacitance.
iii)If the VPP rises particularly fast (>48e6V/s) then it may be
desirable to connect a capacitor from gate to source of theMOSFET to provide a path for the power application tran-sient spike, which is now too fast for the internal clampingmechanism.iv)To limit the peak current during a short circuit, a resistor in
series with the source of the MOSFET may help.
Implementing PWRGD Control
Due to the HV100/HV101’s small footprint, it is possible to createan open drain PWRGD signal using external components andstill maintain a size comparable with the smallest hotswapcontrollers available elsewhere. To accomplish this an externalMOSFET may be used in conjunction with the gate output.Simply use a high impedance divider (10MΩ) sized so that theopen drain PWRGD MOSFET threshold will only be reachedonce the HV100/HV101’s gate voltage rises well above thecurrent limit value required by the external MOSFET passdevice. Alternatively a Zener diode between the gate output andthe PWRGD MOSFET gate set at a voltage higher than themaximum pass element Vt will also work.
Inrush can be calculated from the following formula:
IINRUSH(PEAK) = (CISS / CRSS) * 2.5e3 * CLOAD
This is a surprisingly consistent result because for most MOSFETsof a particular type the ratio of CISS / CRSS is relatively constant(though notice from the plot that there is some variation) evenwhile the absolute value of these and other quantities vary.Based on this, the inrush current will vary primarily with CLOAD.This makes designing with the HV100/HV101 particularly easybecause once the pass element is chosen, the period is fixed andthe inrush varies with CLOAD only.
HV100PWGRD08/26/02 rev.3b
©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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