CD4538BC Dual Precision MonostableOctober 1987Revised April 2002
CD4538BC
Dual Precision Monostable
General Description
The CD4538BC is a dual, precision monostable multivibra-tor with independent trigger and reset controls. The deviceis retriggerable and resettable, and the control inputs areinternally latched. Two trigger inputs are provided to alloweither rising or falling edge triggering. The reset inputs areactive LOW and prevent triggering while active. Precisecontrol of output pulse-width has been achieved using lin-ear CMOS techniques. The pulse duration and accuracyare determined by external components RX and CX. Thedevice does not allow the timing capacitor to dischargethrough the timing pin on power-down condition. For thisreason, no external protection resistor is required in serieswith the timing pin. Input protection from static discharge isprovided on all pins.
Features
sWide supply voltage range: 3.0V to 15VsHigh noise immunity:0.45 VCC (typ.)sLow power TTL compatibility:
Fan out of 2 driving 74L or 1 driving 74LS
sNew formula:
PWOUT = RC (PW in seconds, R in Ohms, C in Farads)s±1.0% pulse-width variation from part to part (typ.)sWide pulse-width range:
1 µs to ∞
sSeparate latched reset inputs
sSymmetrical output sink and source capabilitysLow standby current:5 nA (typ.) @ 5 VDCsPin compatible to CD4528BC
Ordering Code:
Order NumberCD4538BCMCD4538BCWMCD4538BCN
Package Number
M16AM16BN16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150\" Narrow16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300\" Wide16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300\" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection DiagramTruth Table
Inputs
ClearLXXHH
AXHXL
BXXL
OutputsQLLL
QHHH
↓H
↑
Top View
H = HIGH LevelL = LOW Level
↑ = Transition from LOW-to-HIGH↓ = Transition from HIGH-to-LOW = One HIGH Level Pulse = One LOW Level PulseX = Irrelevant
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CD4538BCBlock Diagram
RX and CX are External ComponentsVDD = Pin 16VSS = Pin 8
Logic Diagram
FIGURE 1.
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CD4538BCTheory of Operation
FIGURE 2.
Trigger Operation
The block diagram of the CD4538BC is shown in Figure 1,with circuit operation following.
As shown in Figure 1 and Figure 2, before an input triggeroccurs, the monostable is in the quiescent state with the Qoutput low, and the timing capacitor CX completely chargedto VDD. When the trigger input A goes from VSS to VDD(while inputs B and CD are held to VDD) a valid trigger isrecognized, which turns on comparator C1 and N-Channeltransistor N1(1). At the same time the output latch is set.With transistor N1 on, the capacitor CX rapidly dischargestoward VSS until VREF1 is reached. At this point the outputof comparator C1 changes state and transistor N1 turns off.Comparator C1 then turns off while at the same time com-parator C2 turns on. With transistor N1 off, the capacitor CXbegins to charge through the timing resistor, RX, towardVDD. When the voltage across CX equals VREF2, compara-tor C2 changes state causing the output latch to reset (Qgoes low) while at the same time disabling comparator C2.This ends the timing cycle with the monostable in the qui-escent state, waiting for the next trigger.
A valid trigger is also recognized when trigger input B goesfrom VDD to VSS (while input A is at VSS and input CD is atVDD)(2).
It should be noted that in the quiescent state CX is fullycharged to VDD, causing the current through resistor RX tobe zero. Both comparators are “off” with the total devicecurrent due only to reverse junction leakages. An addedfeature of the CD4538BC is that the output latch is set viathe input trigger without regard to the capacitor voltage.Thus, propagation delay from trigger to Q is independent ofthe value of CX, RX, or the duty cycle of the input wave-form.
Retrigger Operation
The CD4538BC is retriggered if a valid trigger occurs(3) fol-lowed by another valid trigger(4) before the Q output hasreturned to the quiescent (zero) state. Any retrigger, afterthe timing node voltage at pin 2 or 14 has begun to risefrom VREF1, but has not yet reached VREF2, will cause anincrease in output pulse width T. When a valid retrigger isinitiated(4), the voltage at T2 will again drop to VREF1 beforeprogressing along the RC charging curve toward VDD. TheQ output will remain high until time T, after the last validretrigger.
Reset Operation
The CD4538BC may be reset during the generation of theoutput pulse. In the reset mode of operation, an input pulseon CD sets the reset latch and causes the capacitor to befast charged to VDD by turning on transistor Q1(5). Whenthe voltage on the capacitor reaches VREF2, the reset latchwill clear and then be ready to accept another pulse. If theCD input is held low, any trigger inputs that occur will beinhibited and the Q and Q outputs of the output latch willnot change. Since the Q output is reset when an input lowlevel is detected on the CD input, the output pulse T can bemade significantly shorter than the minimum pulse widthspecification.
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CD4538BCFIGURE 3. Retriggerable Monostables Circuitry
FIGURE 4. Non-Retriggerable Monostables Circuitry
FIGURE 5. Connection of Unused Sections
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CD4538BCAbsolute Maximum Ratings(Note 1)
(Note 2)
DC Supply Voltage (VDD)Input Voltage (VIN)
Storage Temperature Range (TS)Power Dissipation (PD)Dual-In-LineSmall OutlineLead Temperature (TL)(Soldering, 10 seconds)
260°C700 mW500 mW
Recommended OperatingConditions (Note 2)
DC Supply Voltage (VDD)Input Voltage (VIN)
Operating Temperature Range (TA)
3 to 15 VDC0 to VDD VDC
−0.5 to +18 VDC
−0.5V to VDD + 0.5 VDC
−65°C to +150°C
−55°C to +125°C
Note 1: “Absolute Maximum Ratings” are those values beyond which thesafety of the device cannot be guaranteed, they are not meant to imply thatthe devices should be operated at these limits. The tables of “Recom-mended Operating Conditions” and “Electrical Characteristics” provide con-ditions for actual device operation.
Note 2: VSS = 0V unless otherwise specified.
DC Electrical Characteristics (Note 2)
SymbolIDD
Parameter
QuiescentDevice Current
VOL
LOW LevelOutput Voltage
VOH
HIGH LevelOutput Voltage
VIL
LOW LevelInput Voltage
VDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15V|IO| < 1 µA
VDD = 5V, VO = 0.5V or 4.5VVDD = 10V, VO = 1.0V or 9.0VVDD = 15V, VO = 1.5V or 13.5V
VIH
HIGH LevelInput Voltage
|IO| < 1 µA
VDD = 5V, VO = 0.5V or 4.5VVDD = 10V, VO = 1.0V or 9.0VVDD = 15V, VO = 1.5V or 13.5V
IOL
LOW LevelOutput Current(Note 3)
IOH
HIGH LevelOutput Current(Note 3)
IINIIN
Input Current,Pin 2 or 14Input CurrentOther Inputs
Note 3: IOH and IOL are tested one output at a time.
ConditionsVIH = VDDVIL = VSS
All Outputs Open|IO| < 1 µA
VIH = VDD, VIL = VSS|IO| < 1 µA
VIH = VDD, VIL = VSS
−55°CMin
Max2040800.050.050.05
4.959.9514.95
1.53.04.0
3.57.011.00.641.64.2−0.6
VIL = VSS
−1.6−4.2
±0.02±0.1
3.57.011.00.511.33.4−0.51−1.3−3.44.959.9514.95Min
+25°CTyp0.0050.0100.015000510152.254.506.752.755.508.250.882.258.8−0.88−2.25−8.8±10−5±10−5±0.05±0.11.53.04.0Max510200.050.050.05
+125°CMin
Max1503006000.050.050.05
4.959.9514.95
1.53.04.0
3.57.011.00.360.92.4−0.36−0.9−2.4
±0.5±1.0
Units
µA
V
V
V
V
VDD = 5V, VO = 0.4VVDD = 10V, VO = 0.5VVD = 15V, VO = 1.5VVDD = 5V, VO = 4.6VVDD = 10V, VO = 9.5VVD = 15V, VO = 13.5V
VIH = VDDVIL = VSS
mA
mAµAµA
VDD = 15V, VIN = 0V or 15VVDD = 15V, VIN = 0V or 15V
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CD4538BCAC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF, and tr = tf = 20 ns unless otherwise specified
SymboltTLH, tTHL
Parameter
Output Transition Time
VDD = 5VVDD = 10VVDD = 15V
tPLH, tPHL
Propagation Delay Time
Trigger Operation—A or B to Q or QVDD = 5VVDD = 10VVDD = 15VReset Operation—CD to Q or QVDD = 5VVDD = 10VVDD = 15V
tWL, tWH
Minimum Input Pulse WidthA, B, or CD
tRR
Minimum Retrigger Time
VDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15V
CINPWOUT
Input Capacitance
Pin 2 or 14Other Inputs
Output Pulse Width (Q or Q)(Note: For Typical Distribution,see Figure 6)
RX = 100 kΩCX = 0.1 µFRX = 100 kΩCX = 10.0 µF
Pulse Width Match betweenCircuits in the Same PackageCX = 0.1 µF, RX = 100 kΩOperating ConditionsRXCX
External Timing ResistanceExternal Timing Capacitance
5.00
(Note 5)No Limit
kΩpF
RX = 100 kΩCX = 0.1 µFRX = 100 kΩCX = 0.002 µF
VDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15V
2082112168.839.029.200.870.890.91
1052262302359.609.8010.000.950.970.99±1±1±1
%
7.524424825410.3710.5910.801.031.051.07
smsµs
025012595353025
500250190706050000
pFnsnsns
300150100
600300220
ns
Conditions
Min
Typ1005040
Max20010080
nsUnits
Note 4: AC parameters are guaranteed by DC correlated testing.
Note 5: The maximum usable resistance RX is a function of the leakage of the Capacitor CX, leakage of the CD4538BC, and leakage due to board layout,surface resistance, etc.
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CD4538BCTypical Applications
FIGURE 6. Typical Normalized Distribution of Units
for Output Pulse Width
FIGURE 9. Typical Pulse Width Error
Versus Temperature
FIGURE 7. Typical Pulse Width Variation as a
Function of Supply Voltage VDD
FIGURE 10. Typical Pulse Width Error
Versus Temperature
FIGURE 8. Typical Total Supply Current VersusOutput Duty Cycle, RX = 100 kΩ, CL = 50 pF,CX = 100 pF, One Monostable Switching Only
FIGURE 11. Typical Pulse Width Versus
Timing RC Product
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CD4538BCTest Circuits and Waveforms
FIGURE 12. Switching Test Waveforms
*CL = 50 pF
Input Connections
CharacteristicstPLH, tPHL, tTLH, tTHLPWOUT, tWH, tWLtPLH, tPHL, tTLH, tTHLPWOUT, tWH, tWLtPLH(R), tPHL(R),tWH, tWL
PG3
PG1
PG2
VDD
VSS
PG2
CDVDD
APG1
BVDD
*Includes capacitance of probes, wiring, and fixture parasitic
Note: Switching test waveforms for PG1, PG2, PG3 are shown in Figure 12.
FIGURE 13. Switching Test Circuit
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CD4538BCTest Circuits and Waveforms (Continued)
RX = RX′ = 100 kΩCX = CX′ = 100 pFC1 = C2 = 0.1 µF
Duty Cycle = 50%
FIGURE 14. Power Dissipation Test
Circuit and Waveforms
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CD4538BCPhysical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150\" Narrow
Package Number M16A
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300\" Wide
Package Number M16B
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CD4538BC Dual Precision MonostablePhysical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300\" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.
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2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.
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