Freescale Semiconductor
Data Sheet: Advance Information
MCF52235DSRev. 0, 04/2006
MCF52235 ColdFire® Microcontroller Data Sheet
Supports MCF52235, MCF52234, MCF52233, MCF52231, & MCF52230
By: Microcontroller Division
The MCF52235 is a member of the ColdFire® family ofreduced instruction set computing (RISC)microprocessors. This hardware specification providesan overview of the 32-bit MCF52235 microcontroller,focusing on its highly integrated and diverse feature set. This 32-bit device is based on the Version 2 ColdFirecore operating at a frequency up to 60 MHz, offeringhigh performance and low power consumption. On-chipmemories connected tightly to the processor core include256 Kbytes of Flash and 32 Kbytes of static randomaccess memory (SRAM). On-chip modules include:•V2 ColdFire core providing 56 Dhrystone 2.1 MIPS @ 60 MHz executing out of on-chip Flash memory using enhanced multiply accumulate (EMAC) and hardware divider.
•Enhanced Multiply Accumulate Unit (EMAC) and hardware divide module
•Cryptographic Acceleration Unit (CAU) coprocessor
•Fast Ethernet Controller (FEC)
•On-chip Ethernet Transceiver (ePHY)
Table of Contents
1MCF52235 Family Configurations.......................21.1Block Diagram...................................................31.2Features.............................................................41.3Part Numbers and Packaging..........................161.4Package Pinouts..............................................171.5Reset Signals..................................................241.6PLL and Clock Signals....................................241.7Mode Selection................................................241.8External Interrupt Signals................................241.9Queued Serial Peripheral Interface (QSPI).....251.11I2C I/O Signals.................................................271.12UART Module Signals.....................................271.13DMA Timer Signals..........................................271.16Pulse Width Modulator Signals........................281.17Debug Support Signals....................................281.18EzPort Signal Descriptions..............................301.19Power and Ground Pins...................................3023
Preliminary Electrical Characteristics................31Mechanical Outline Drawings............................45
This document contains information on a new product. Specifications and information hereinare subject to change without notice.
©Freescale Semiconductor, Inc., 2006. All rights reserved.• Preliminary
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
•••••••••••••••
FlexCAN controller area network (CAN) module
Three universal asynchronous/synchronous receiver/transmitters (UARTs)Inter-integrated circuit (I2C™) bus controller Queued serial peripheral interface (QSPI) module
Eight-channel 12-bit fast analog-to-digital converter (ADC)Four channel direct memory access (DMA) controller
Four 32-bit input capture/output compare timers with DMA support (DTIM)
Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width modulation (PWM) and pulse accumulation
Eight/Four-channel 8/16-bit pulse width modulation timers (two adjacent 8-bit PWMs can be concatenated to form a single 16-bit timer)Two 16-bit periodic interrupt timers (PITs)
Real-time clock (RTC) module
Programmable software watchdog timer
Two interrupt controllers providing every peripheral with a unique selectable-priority interrupt vector plus seven external interrupts with fixed levels/priorities
Clock module with support for crystal or external oscillator and integrated phase locked loop (PLL)
Test access/debug port (JTAG, BDM)
1MCF52235 Family Configurations
Table1. MCF52235 Family Configurations
Module
52230x
52231x
52233x60 MHz56
128/32 Kbytes
xx--xx
xx-xxx
xx--xx
256/32 Kbytes
xx-xxx
xxxxxx
52234x
52235x
ColdFire Version 2 Core with MAC (Multiply-Accumulate Unit)System Clock
Performance (Dhrystone 2.1 MIPS)Flash / Static RAM (SRAM)Interrupt Controllers (INTC0/INTC1)Fast Analog-to-Digital Converter (ADC)Random Number Generator and Crypto Acceleration Unit (CAU)FlexCAN 2.0B Module
Fast Ethernet Controller (FEC) with on-chip interface (ePHY)
Four-channel Direct-Memory Access (DMA)
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
2
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
Table1. MCF52235 Family Configurations (continued)
Module
Software Watchdog Timer (WDT)Programmable Interrupt Timer Four-Channel General Purpose Timer32-bit DMA TimersQSPIUART(s)I2C
Eight/Four-channel 8/16-bit PWM TimerGeneral Purpose I/O Module (GPIO)Chip Configuration and Reset Controller Module
Background Debug Mode (BDM)JTAG - IEEE 1149.1 Test Access Port1Package
52230x2x4x3xxxxxx80-pin LQFP112-pin LQFP
52231x2x4x3xxxxxx80-pin LQFP112-pin LQFP
52233x2x4x3xxxxxx80-pin LQFP112-pin LQFP
52234x2x4x3xxxxxx80-pin LQFP112-pin LQFP121 MAPBGA
52235x2x4x3xxxxxx112-pin LQFP121 MAPBGA
1
NOTES:
The full debug/trace interface is available only on the 112- and 121-pin packages. A reduced debug interface is bonded on the 80-pin package.
1.1Block Diagram
The MCF52235 (or its variants) come in 80- and 112-pin low-profile quad flat pack packages (LQFP) anda 121 MAPBGA, and operates in single-chip mode only. Figure1 shows a top-level block diagram of theMCF52235.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
3
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
EPHY_TXEzPDEPHY_RXEzPQ
EzPort
EzPCKEzPCS
InterruptController 1
InterruptController 2
PADI – Pin MuxingICOCnQSPI_DIN,QSPI_DOUTQSPI_SCK,QSPI_PCSnI2C_SDAI2C_SCLUnTXDUnRXDUnRTSUnCTSDTINn/DTOUTnCANRXCANTXPWMn
EPHYArbiter
ControllerFast Ethernet
(FEC)4 CH DMATo/From PADI
UART0UART1UART2
I2C
QSPI
DTIM0DTIM1DTIM2DTIM3
RTC
JTAG_ENMUX
V2 ColdFire CPU
JTAGTAP
IFP
OEP
CAUEMAC
PMM
AN[7:0]ADC
32 KbytesSRAM(4Kx16)x4256 KbytesFlash(32Kx16)x4
PORTS(GPIO)
CIM
RSTINRSTOUT
VRHVRL
EdgePort 1
EdgePort 2
PLL CLKGEN
EXTALXTALCLKOUT
FlexCANPIT1PWM
RNGAPIT0GPT
To/From Interrupt ControllerFigure1. MCF52235 Block Diagram
1.2Features
This document contains information on a new product under development. Freescale reserves the right tochange or discontinue this product without notice. Specifications and information herein are subject tochange without notice.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
4
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
1.2.1
•
Feature Overview
Version 2 ColdFire variable-length RISC processor core—Static operation
—32-bit address and data path on-chip—Up to 60MHz processor core frequency
—Sixteen general-purpose 32-bit data and address registers
—Implements ColdFire ISA_A+ with extensions to support the user stack pointer register, and 4
new instructions for improved bit processing
—Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support32-bit signal processing algorithms
—Cryptography Acceleration Unit (CAU)
–Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions–FIPS-140 compliant random number generator
–Support for DES, 3DES, AES, MD5, and SHA-1 algorithms—Illegal instruction decode that allows for 68K emulation supportSystem debug support
—Real time trace for determining dynamic execution path —Background debug mode (BDM) for in-circuit debugging
—Real time debug support, with four user-visible hardware breakpoint registers (PC and address
with optional data) that can be configured into a 1- or 2-level triggerOn-chip memories
—32 Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus
masters (e.g., DMA) with standby power supply support
—256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accessesPower management
—Fully static operation with processor sleep and whole chip stop modes
—Very rapid response to interrupts from the low-power sleep mode (wake-up feature)—Software visible clock enable/disable for each peripheralFast Ethernet Controller (FEC)
—10/100 BaseT/TX capability, half duplex or full duplex—On-chip transmit and receive FIFOs—Built-in dedicated DMA controller—Memory-based flexible descriptor rings
•
•
•
•
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
5
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
•
•
•
On-chip Ethernet Transceiver (ePHY)—Digital adaptive equalization—Supports auto-negotiation—Baseline wander correction
—Full-/Half-duplex support in all modes—Loopback modes
—Supports MDIO preamble suppression—Jumbo packet
FlexCAN 2.0B Module
—Based on and includes all existing features of the Freescale TOUCAN module—Full implementation of the CAN protocol specification version 2.0B–Standard Data and Remote Frames (up to 109 bits long)–Extended Data and Remote Frames (up to 127 bits long)–0-8 bytes data length
–Programmable bit rate up to 1 Mbit/sec
—Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length each, configurable as Rx or Tx, all supporting standard and extended messages—Unused Message Buffer space can be used as general purpose RAM space—Listen only mode capability—Content-related addressing
—No read/write semaphores required
—Three programmable mask registers: global (for MBs 0-13), special for MB14 and special for
MB15
—Programmable transmit-first scheme: lowest ID or lowest buffer number—“Time stamp” based on 16-bit free-running timer
—Global network time, synchronized by a specific message—Programmable I/O modes—Maskable interrupts
Three Universal Asynchronous/synchronous Receiver Transmitters (UARTs)—16-bit divider for clock generation—Interrupt control logic—Maskable interrupts—DMA support
—Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity—Up to 2 stop bits in 1/16 increments—Error-detection capabilities
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
6PreliminaryFreescale Semiconductor
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
—Modem support includes request-to-send (URTS) and clear-to-send (UCTS) lines for two UARTs
—Transmit and receive FIFO buffers•
I2C Module
—Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads—Fully compatible with industry-standard I2C bus
—Master or slave modes support multiple masters
—Automatic interrupt generation with programmable levelQueued Serial Peripheral Interface (QSPI)
—Full-duplex, three-wire synchronous transfers—Up to four chip selects available—Master mode operation only—Programmable master bit rates—Up to 16 pre-programmed transfersFast Analog-to-Digital Converter (ADC)—8 analog input channels—12-bit resolution
—Minimum 2.25 µS conversion time
—Simultaneous sampling of two channels for motor control applications—Single-scan or continuous operation
—Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit
—Unused analog channels can be used as digital I/OFour 32-bit DMA Timers
—16.7-ns resolution at 60 MHz
—Programmable sources for clock input, including an external clock option—Programmable prescaler
—Input-capture capability with programmable trigger edge on input pin—Output-compare with programmable mode for the output pin—Free run and restart modes
—Maskable interrupts on input capture or reference-compare—DMA trigger capability on input capture or reference-compareFour-channel general purpose timers—16-bit architecture
—Programmable prescaler
—Output pulse widths variable from microseconds to seconds
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
7
•
•
•
•
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
•
—Single 16-bit input pulse accumulator
—Toggle-on-overflow feature for pulse-width modulator (PWM) generation—One dual-mode pulse accumulation channelPulse-width modulation timer
—Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution—Programmable period and duty cycle
—Programmable enable/disable for each channel—Software selectable polarity for each channel
—Period and duty cycle are double buffered. Change takes effect when the end of the current period is reached (PWM counter reaches zero) or when the channel is disabled. —Programmable center or left aligned outputs on individual channels
—Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies—Emergency shutdown
Two Periodic Interrupt Timers (PITs)—16-bit counter
—Selectable as free running or count downReal-Time Clock (RTC)
—Maintains system time-of-day clock
—Provides stopwatch and alarm interrupt functionsSoftware Watchdog Timer—32-bit counter
—Low power mode supportClock Generation Features—25 MHz crystal input
—On-chip PLL can generate core frequencies up to maximum 60MHz operating frequency—Provides clock for integrated ePHYDual Interrupt Controllers (INTC0/INTC1)
—Support for multiple interrupt sources organized as follows:–Fully-programmable interrupt sources for each peripheral–7 fixed-level interrupt sources–Seven external interrupt signals
—Unique vector number for each interrupt source
—Ability to mask any individual interrupt source or all interrupt sources (global mask-all)—Support for hardware and software interrupt acknowledge (IACK) cycles—Combinatorial path to provide wake-up from low power modes
•
•
•
•
•
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
8
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
•
DMA Controller
—Four fully programmable channels
—Dual-address transfer support with 8-, 16- and 32-bit data capability along with support for 16-byte (4 X 32-bit) burst transfers
—Source/destination address pointers that can increment or remain constant
—24-bit byte transfer counter per channel
—Auto-alignment transfers supported for efficient block movement—Bursting and cycle steal support
—support for channel-to-channel linking
—Software-programmable DMA channel selections in the UARTs (3) and 32-bit timers (4)Reset
—Separate reset in and reset out signals
—Seven sources of reset:–Power-on reset (POR)–External–Software–Watchdog–Loss of clock–Loss of lock
–Low-voltage detection (LVD)
—Status flag indication of source of last resetChip Integration Module (CIM)
—System configuration during reset—Selects one of six clock modes
—Configures output pad drive strength
—Unique part identification number and part revision numberGeneral Purpose I/O interface
—Up to 73 bits of general purpose I/O
—Bit manipulation supported via set/clear functions—Unused peripheral pins may be used as extra GPIOJTAG support for system level board testing
•
•
•
•
1.2.2V2 Core Overview
The Version 2 ColdFire processor core is comprised of two separate pipelines that are decoupled by aninstruction buffer. The two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-addressgeneration and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
9
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP). The OEP includestwo pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage(AGEX) performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire Instruction Set Architecture Revision A+ (see the ColdFire FamilyProgrammer’s Reference Manual for instruction set details) which includes support for a separate userstack pointer register and four new instructions to assist in bit processing. Additionally, the MCF52235core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing capabilities.The MAC implements a 4-stage arithmetic pipeline, optimized for 32 x 32 bit operations, with support forfour 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned integers as wellas signed fractional operands and a complete set of instructions to process these data types. The EMACprovides superb support for execution of DSP operations within the context of a single processor at aminimal hardware cost.
1.2.3Debug Module
The ColdFire processor core debug interface is provided to support system debugging in conjunction withlow-cost debug and emulator development tools. Through a standard debug interface users can accessdebug information, and on 112- and 121-lead packages real-time tracing capability is provided. Thisallows the processor and system to be debugged at full speed without the need for costly in-circuitemulators. The debug interface is a superset of the BDM interface provided on Freescale’s 683xx familyof parts. The MCF52235 supports Revision B+ of the ColdFire debug architecture (DEBUG_B+).The on-chip breakpoint resources include a total of nine programmable 32-bit registers: two addressregisters, two data registers (one data register and one data mask register), four 32-bit PC registers and onePC mask register. These registers can be accessed through the dedicated debug serial communicationchannel or from the processor’s supervisor mode programming model. The breakpoint registers can beconfigured to generate triggers by combining the address, data, and PC conditions in a variety of single-or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate adebug interrupt exception.
The MCF52235’s interrupt servicing options during emulator mode allow real-time critical interruptservice routines to be serviced while processing a debug interrupt event, thereby ensuring that the systemcontinues to operate even during debugging.
To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data(DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operanddata, and branch target addresses defining processor activity at the CPU’s clock rate. The MCF52235includes a new debug signal, ALLPST. This signal is the logical ‘AND’ of the processor status (PST[3:0])signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).
The full debug/trace interface is available only on the 112- and 121-pin packages. However, every productfeatures the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
1.2.4JTAG
The MCF52235 supports circuit board test strategies based on the Test Technology Committee of IEEEand the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
10
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bitboundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins intoone shift register. Test logic, implemented using static logic design, is independent of the device systemlogic.
The MCF52235 implementation can do the following:•••••
Perform boundary-scan operations to test circuit board electrical continuity
Sample MCF52235 system pins during operation and transparently shift out the result in the boundary scan register
Bypass the MCF52235 for a given circuit board test by effectively reducing the boundary-scan register to a single bit
Disable the output drive to pins during circuit-board testingDrive output pins to stable levels
1.2.5
1.2.5.1
On-Chip Memories
SRAM
The SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can accessin a single cycle. The location of the memory block can be set to any 32-Kbyte boundary within the4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as thesystem stack. Because the SRAM module is physically connected to the processor's high-speed local bus,it can quickly service core-initiated accesses or memory-referencing commands from the debug module.The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it idealfor implementing applications with double-buffer schemes, where the processor and a DMA deviceoperate in alternate regions of the SRAM to maximize system performance.
1.2.5.2Flash
The ColdFire Flash Module (CFM) is a non-volatile memory (NVM) module that connects to theprocessor’s high-speed local bus. The CFM is constructed with four banks of 32K x 16-bit Flash arrays togenerate 256 Kbytes of 32-bit Flash memory. These arrays serve as electrically erasable andprogrammable, non-volatile program and data memory. The Flash memory is ideal for program and datastorage for single-chip applications, allowing for field reprogramming without requiring an external highvoltage source. The CFM interfaces to the ColdFire core through an optimized read-only memorycontroller which supports address speculation and interleaved accesses from the 2-cycle Flash arrays forimproved performance. For operation at reduced core frequencies, the access time can be decreased (underprogram control) to a single-cycle access. A backdoor mapping of the Flash memory is used for allprogram, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memorymay also be programmed via the EzPort, which is a serial Flash programming interface that allows theFlash to be read, erased and programmed by an external controller in a format compatible with most SPIbus Flash memory chips. This allows easy device programming via Automated Test Equipment or bulkprogramming tools.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
11
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
1.2.6Power Management
The MCF52235 incorporates several low power modes of operation which are entered under programcontrol and exited by several external trigger events. An integrated power-on reset (POR) circuit monitorsthe input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD)monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below theLVD trip point.
1.2.7Fast Ethernet Controller (FEC)
The integrated Fast Ethernet Controller (FEC) performs the full set of IEEE® 802.3/Ethernet CSMA/CDmedia access control and channel interface functions. The FEC connects through the on-chip transceiver(ePHY) which provides the physical layer interface.
1.2.8Ethernet Physical Interface (ePHY)
The ePHY is an IEEE 802.3 compliant 10/100 Ethernet physical transceiver. The ePHY can be configuredto support 10BASE-T or 100BASE-TX applications. The ePHY is configurable via internal registers.There are five basic modes of operation for the ePHY:•Power down/initialization•Auto-negotiate•10BASE-T•100BASE-TX•Low-power
1.2.9Cryptography Acceleration Unit
The MCF52235 device incorporates two hardware accelerators for cryptographic functions. First, theCAU is a coprocessor tightly-coupled to the V2 ColdFire core that implements a set of specializedoperations to increase the throughput of software-based encryption and message digest functions,specifically the DES, 3DES, AES, MD5 and SHA-1 algorithms. Second, a random number generatorprovides FIPS-140 compliant 32-bit values to security processing routines. Both modules supply criticalacceleration to software-based cryptographic algorithms at a minimal hardware cost.
1.2.10FlexCAN
The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol partsA and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specificrequirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation ofFlexCAN has 16 message buffers.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
12
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
1.2.11UARTs
The MCF52235 has three full-duplex UARTs that function independently. The three UARTs can beclocked by the system bus clock, eliminating the need for an external clock source. On smaller packages,the third UART is multiplexed with other digital I/O functions.
1.2.12I2C Bus
The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchangeand minimizes the interconnection between devices. This bus is suitable for applications requiringoccasional communications over a short distance between many devices on a circuit board.
1.2.13QSPI
The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface withqueued transfer capability. It allows up to 16 transfers to be queued at once, minimizing the need for CPUintervention between transfers.
1.2.14ADC
The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold(S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessiblebuffers for further processing.
The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, orperform a programmed scan sequence repeatedly until manually stopped.
The ADC can be configured for either sequential or simultaneous conversion. When configured forsequential conversions, up to eight channels can be sampled and stored in any order specified by thechannel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled.During a simultaneous conversion, both S/H circuits are used to capture two different channels at the sametime. This configuration requires that a single channel may not be sampled by both S/H circuitssimultaneously.
Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measuresbelow the low threshold limit or above the high threshold limit set in the limit registers) or at severaldifferent zero crossing conditions.
1.2.15DMA Timers (DTIM0–DTIM3)
There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3)on the MCF52235. Each module incorporates a 32-bit timer with a separate register set for configurationand control. The timers can be configured to operate from the system clock or from an external clocksource using one of the DTINx signals. If the system clock is selected, it can be divided by 16 or 1. Theinput clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counterregister (TCRn). Each of these timers can be configured for input capture or reference (output) comparemode. Timer events may optionally cause interrupt requests or DMA transfers.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
13
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
1.2.16General Purpose Timer (GPT)
The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmablecounter driven by a 7-stage programmable prescaler. Each of the four channels can be configured for inputcapture or output compare. Additionally, one of the channels, channel 3, can be configured as a pulseaccumulator.
A timer overflow function allows software to extend the timing capability of the system beyond the 16-bitrange of the counter. The input capture and output compare functions allow simultaneous input waveformmeasurements and output waveform generation. The input capture function can capture the time of aselected transition edge. The output compare function can generate output waveforms and timer softwaredelays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.
1.2.17Periodic Interrupt Timers (PIT0 and PIT1)
The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regularintervals with minimal processor intervention. Each timer can either count down from the value written inits PIT modulus register, or it can be a free-running down-counter.
1.2.18Pulse Width Modulation Timers
The MCF52235 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and dutycycle as well as a dedicated counter. Each of the modulators can create independent continuous waveformswith software-selectable duty rates from 0% to 100%. The PWM outputs have programmable polarity, andcan be programmed as left aligned outputs or center aligned outputs. For higher period and duty cycleresolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form asingle 16-bit channel. The module can thus be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bitchannels.
1.2.19Real-Time Clock (RTC)
The Real-Time Clock (RTC) module maintains the system (time-of-day) clock and provides stopwatch,alarm, and interrupt functions. It includes full clock features: seconds, minutes, hours, days and supportsa host of time-of-day interrupt functions along with an alarm interrupt.
1.2.20Software Watchdog Timer
The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog counteris a free-running down-counter that generates a reset on underflow. To prevent a reset, software mustperiodically restart the countdown.
1.2.21Phase Locked Loop (PLL)
The clock module supports an external crystal oscillator and includes a phase-locked loop (PLL), reducedfrequency divider (RFD), low-power divider status/control registers, and control logic. In order to improve
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
14
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
noise immunity the PLL has its’ own power supply inputs: VDDPLL and VSSPLL. All other circuits arepowered by the normal supply pins, VDD and VSS.
1.2.22Interrupt Controller (INTC0/INTC1)
There are two interrupt controllers on the MCF52235. These interrupt controllers are organized as sevenlevels with up to nine interrupt sources per level. Each interrupt source has a unique interrupt vector, andprovide each peripheral with all necessary interrupts. Each internal interrupt has a programmable level[1-7] and priority within the level. The seven external interrupts have fixed levels/priorities.
1.2.23DMA Controller
The Direct Memory Access (DMA) Controller Module provides an efficient way to move blocks of datawith minimal processor interaction. The DMA module provides four channels (DMA0-DMA3) that allowbyte, word, longword or 16-byte burst line transfers. These transfers are triggered by software explicitlysetting a DCRn[START] bit or by the assertion of a DMA request from any number of on-chip peripherals.The DMA controller supports dual address transfers to on-chip devices.
1.2.24Reset
The reset controller determines the source of reset, asserts the appropriate reset signals to the system, andkeeps track of what caused the last reset. There are six sources of reset:•External reset input•Power-on reset (POR)•Watchdog timer
•Phase locked-loop (PLL) loss of lock•PLL loss of clock•SoftwareRegisters provide status flags indicating the last source of reset and a control bit for software assertion ofthe RSTO pin.1.2.25GPIO
All of the pins associated with the external bus interface may be used for several different functions. When not used this, all of the pins may be used as general-purpose digital I/O pins. In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported.
The digital I/O pins on the MCF52235 are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pins.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
15
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
1.3Part Numbers and Packaging
Table2. Part Number Summary
Flash / SRAM
Key Features
Package80-pin TQFP112-pin LQFP80-pin TQFP112-pin LQFP80-pin TQFP112-pin LQFP80-pin TQFP112-pin LQFP121 MAPBGA112-pin LQFP121 MAPBGA
Speed60 MHz60 MHz60 MHz60 MHz
128 Kbytes / 32 Kbytes3 UARTs, I2C, QSPI, A/D, FEC ePHY, DMA,
16-/32-bit PWM Timers 128 Kbytes / 32 Kbytes3 UARTs, I2C, QSPI, A/D, FEC ePHY, DMA,
16-/32-bit PWM Timers, CAN256 Kbytes / 32 Kbytes3 UARTs, I2C, QSPI, A/D, FEC ePHY, DMA,
16-/32-bit PWM Timers256 Kbytes / 32 Kbytes
3 UARTs, I2C, QSPI, A/D, FEC, ePHY, DMA, 16-/32-bit PWM Timers, CAN
Part NumberMCF52230MCF52231MCF52233MDCF52234
MCF52235
256 Kbytes / 32 Kbytes3 UARTs, I2C, QSPI, A/D, CAU, FEC, DMA,
ePHY, 16-/32-bit PWM Timers, CAN
60 MHz
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
16
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
1.4Package Pinouts
Figure2 shows the pinout configuration for the 80-Lead TQFP.
I2C_SDATCLK/PSTCLK
TMS/BKPTRCON/EZPCS
TDI/DSITDO/DSOTRST/DSCLK
ALLPSTTIN0/TOUT0TIN1/TOUT1
VDDX1VSSX1JTAG_ENTIN2/TOUT2TIN3/TOUT3
U1_RTSU1_CTSU0_RTSU0_CTSSYNCBSYNCA
8079787776757473727170696867666564636261I2C_SCLGPT0GPT1GPT2GPT3VDD1VSS1VSSAVRLVRHVDDAAN0AN1AN2AN3AN7AN6AN5AN41234567891011121314151617181920
80-LeadTQFP-EP
6059585756555453525150494847464544434241ACT_LEDLINK_LEDVDDRSPD_LEDPHY_VSSRXPHY_VDDRXPHY_RXNPHY_RXPPHY_VSSTXPHY_TXNPHY_TXPPHY_VDDTXPHY_VDDAPHY_VSSAPHY_RBIASVDD2VSS2DUPLEDCOLLEDIRQ11
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
17
U0_RXDU0_TXDU1_RXDU1_TXDQSPI_DINQSPI_DOUTQSPI_SCKQSPI_CS0IRQ4VSSX2VDDX2RSTIVDDPLLRSTOVSSPLLEXTALXTALTESTIRQ1IRQ12122232425262728293031323334353637383940Figure2. 80-Lead TQFP Pin Assignments
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
Figure3 shows the pinout configuration for the 112-Lead LQFP.
111110109108107106105104103102101100999897969594939291908988878685112I2C_SDAI2C_SCLGPT0GPT1GPT2GPT3IRQ15IRQ14PWM7PWM5VDD1VSS1PWM3PWM1IRQ13IRQ12VSSAVRLVRHVDDAAN0AN1AN2AN3AN7AN6AN5AN418
IRQ10U0_RXDU0_TXDU1_RXDU1_TXDQSPI_DOUTQSPI_DINQSPI_SCKQSPI_CS0QSPI_CS1QSPI_CS2QSPI_CS3IRQ4VSSX2VDDX2RSTIVDDPLLRSTOVSSPLLEXTALXTALTESTPL6/TXLEDPL5/RXLEDIRQ3IRQ2IRQ1IRQ7Figure3. 112-Lead LQFP Pin Assignments
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Preliminary
Freescale Semiconductor
29303132333435363738394041424344454647484950515253545556TCLK/PSTCLKTMS/BKPTRCON/EZPCS
TDI/DSITDO/DSOTRST/DSCLK
ALLPSTTIN0/TOUT0TIN1/TOUT1
IRQ8IRQ9DDATA3DDATA2VDDX1VSSX1DDATA1DDATA0JTAG_EN
IRQ6IRQ5TIN2/TOUT2TIN3/TOUT3
U1_RTSU1_CTSU0_RTSU0_CTSSYNCBSYNCA12345678910111213141516171819202122232425262728
112-Lead LQFP
84838281807978777675747372717069686766656463626160595857ACTLEDLNKLEDVDDRSPDLEDPST3PST2PST1PST0
PHY_VSSRXPHY_VDDRXPHY_RXNPHY_RXPPHY_VSSTXPHY_TXNPHY_TXPPHY_VDDTXPHY_VDDAPHY_VSSAPHY_RBIASVDD2VSS2U2_TXDU2_RXDU2_CTSU2_RTSDUPLEDCOLLEDIRQ11
元器件交易网www.cecb2b.com
Freescale SemiconductorTable3. Pin Functions by Primary and Alternate Purpose
PinPrimarySecondaryTertiary QuaternaryDrive
Pull-up / GroupFunctionFunction
Function
FunctionStrength /
Wired OR
2Pin on121 Pin on 112 Pin on 80 Control1Control
Pull-downMAPBGALQFPLQFP
Notes
ADC
AN7——PAN[0]Low———8864AN6——PAN[1]Low———8763AN5——PAN[2]Low———8662AN4
——PAN[3]Low———8561MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0AN3——PAN[4]Low———8965AN2——PAN[5]Low———9066AN1——PAN[6]Low———9167AN0——PAN[7]Low———9268SYNCACANTX3FEC_MDIOPAS[3]PDSR[39]———2820PreliminarySYNCBCANRX3
FEC_MDC
PAS[2]PDSR[39]———2719VDDA———N/AN/A——9369VSSA———N/AN/A——9672VRH———N/AN/A——9470VRL
———N/AN/A——9571Clock EXTAL———N/AN/A——4836Generation
XTAL———N/AN/A——4937VDDPLL———N/AN/A——4533
VSSPLL
———N/AN/A——4735Debug ALLPST———High———77Data
DDATA[3:0]——PDD[7:4]High———12,13,
—16,17PST[3:0]
—
—
PDD[3:0]
High
—
—
—
80,79,—
78,77
19MCF52235 Family Configurations元器件交易网www.cecb2b.com
20PinPrimarySecondaryTertiary QuaternaryDrive
Wired OR
Pull-up / GroupFunctionFunction
Function
FunctionStrength /
2Pin on121 Pin on 112 Pin on 80 Control1Control
Pull-downMAPBGALQFPLQFP
Notes
Ethernet ACTLED——PSD[0]PDSR[32]PWOR[8]——8460LEDs
COLLED——PSD[4]PDSR[36]PWOR[12]——5842DUPLED——PSD[3]PDSR[35]PWOR[11]——5943LNKLED——PSD[1]PDSR[33]PWOR[9]——8359SPDLED——PSD[2]PDSR[34]PWOR[10]——8157RXLED——PSD[5]PDSR[37]PWOR[13]——52—TXLED
——PSD[6]PDSR[38]
PWOR[14]
—
—51—Ethernet
PHY_RBIAS——————6646PHY
PHY_RXN——————7454PHY_RXP——————7353PreliminaryMCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0PHY_TXN——————7151PHY_TXP————
——7050PHY_VDDA———N/A—6848PHY_VDDRX———N/A—7555PHY_VDDTX———N/A—6949PHY_VSSA———N/A—6747PHY_VSSRX———N/A—7656PHY_VSSTX
———N/A—
7252I2C
SCLCANTX3TXD2PAS[1]PDSR[0]—pull-up4—11179SDA
CANRX3
RXD2
PAS[0]
PDSR[0]—
pull-up4
—
112
80
Freescale SemiconductorMCF52235 Family Configurations元器件交易网www.cecb2b.com
Freescale SemiconductorPinPrimarySecondaryTertiary QuaternaryDrive
Wired OR
Pull-up / GroupFunctionFunction
Function
FunctionStrength /
2Pin on121 Pin on 112 Pin on 80 Control1Control
Pull-downMAPBGALQFPLQFP Notes
Interrupts
IRQ15——PGP[7]PSDR[47]—pull-up4—106—IRQ14——PGP[6]PSDR[46]—pull-up4—105—IRQ13——PGP[5]PSDR[45]—pull-up4—98—IRQ12——PGP[4]PSDR[44]—pull-up4—97—IRQ11——PGP[3]PSDR[43]—pull-up4—57—IRQ10——PGP[2]PSDR[42]—pull-up4—29—IRQ9——PGP[1]PSDR[41]—pull-up4—11—IRQ8——PGP[0]PSDR[40]—pull-up4—10—IRQ7——PNQ[7]Low—pull-up4—5640IRQ6—FEC_RXERPNQ[6]Low—pull-up4—19—PreliminaryMCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0IRQ5—FEC_RXD[1]
PNQ[5]Low—pull-up4—20—IRQ4——PNQ[4]Low—pull-up4—4129IRQ3—FEC_RXD[2]PNQ[3]Low—pull-up4—53—IRQ2—FEC_RXD[3]PNQ[2]Low—pull-up4—54—IRQ1SYNCAPWM1PNQ[1]High—pull-up4—5539JTAG/BDMJTAG_EN———N/AN/Apull-down—1812TCLK/
CLKOUT——High—pull-up5—11
PSTCLKTDI/DSI———N/AN/Apull-up5
—44TDO/DSO———HighN/A——55TMS———N/AN/Apull-up5—22/BKPTTRST———N/AN/Apull-up5—66/DSCLK
Mode RCON/—
—
—
N/A
N/A
pull-up
—
3
3
SelectionEZPCS
21MCF52235 Family Configurations元器件交易网www.cecb2b.com
22PinPrimarySecondaryTertiary QuaternaryDrive
Pull-up / Pin on121 Pin on 112 Pin on 80 GroupFunctionFunction
Function
FunctionStrength /
Wired OR
Control1Control
Pull-down2MAPBGALQFPLQFP
Notes
PWM
PWM7——PTD[3]PDSR[31]———104—PWM5——PTD[2]PDSR[30]———103—PWM3——PTD[1]PDSR[29]———100—PWM1
——PTD[0]PDSR[28]———99—QSPI
QSPI_DIN/
CANRX3RXD1PQS[1]PDSR[2]PWOR[4]——3525EZPDQSPI_DOUT/
CANTX3TXD1PQS[0]PDSR[1]PWOR[5]——3426EZPQQSPI_SCK/SCLRTS1PQS[2]PDSR[3]PWOR[6]
pull-up6
—3627EZPCKQSPI_CS3SYNCASYNCBPQS[6]PDSR[7]———40—PreliminaryMCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0QSPI_CS2——PQS[5]PDSR[6]———39—QSPI_CS1——PQS[4]PDSR[5]———38—QSPI_CS0
SDACTS1PQS[3]PDSR[4]PWOR[7]pull-up6—3758Reset7
RSTI———N/AN/Apull-up7
—4432RSTO———high———4634TestTEST———N/AN/Apull-down—5038Timers, GPT3FEC_TXD[3]PWM7PTA[3]PDSR[23]PWOR[23]pull-up8—1077516-bit
GPT2FEC_TXD[2]PWM5PTA[2]PDSR[22]PWOR[22]pull-up8—10876GPT1FEC_TXD[1]PWM3PTA[1]PDSR[21]PWOR[21]pull-up8—10977GPT0
FEC_TXERPWM1PTA[0]PDSR[20]PWOR[20]pull-up8
—11078Freescale SemiconductorTimers, TIN3TOUT3PWM6PTC[3]PDSR[19]PWOR[19]——221432-bit
TIN2TOUT2PWM4PTC[2]PDSR[18]PWOR[18]——2113TIN1TOUT1PWM2PTC[1]PDSR[17]PWOR[17]——99TIN0
TOUT0
PWM0
PTC[0]
PDSR[16]
PWOR[16]
—
—
8
8
MCF52235 Family Configurations元器件交易网www.cecb2b.com
Freescale SemiconductorPinPrimarySecondaryTertiary QuaternaryDrive
Pull-up / Pin on121 Pin on 112 Pin on 80 GroupFunctionFunctionFunctionFunctionStrength /
Wired OR
Notes
Control1Control
Pull-down2MAPBGALQFPLQFP
UART 0
CTS0CANRX3FEC_RXCLKPUA[3]PDSR[11]———2618RTS0CANTX3
FEC_RXDVPUA[2]PDSR[10]———2517RXD0—FEC_RXD[0]PUA[1]PDSR[9]PWOR[0]——3021TXD0
—FEC_CRSPUA[0]PDSR[8]PWOR[1]
——3122UART 1CTS1SYNCARXD2PUB[3]PDSR[15]———2416RTS1SYNCBTXD2PUB[2]PDSR[14]———2315RXD1—FEC_TXD[0]PUB[1]PDSR[13]PWOR[2]——3223TXD1
—FEC_COL
PUB[0]PDSR[12]PWOR[3]
——3324UART 2CTS2——PUC[3]PDSR[27]———61—RTS2——PUC[2]PDSR[26]———60—PreliminaryMCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0RXD2——PUC[1]PDSR[25]———62—TXD2
—
—PUC[30]PDSR[24]———63—FlexCANCANRXFEC_MDIOPAS[3]PDSR[39]—————See Note3CANTX
FEC_MDC
PAS[2]PDSR[39]———
——See Note3
VDD9VDD———N/AN/A—14,43,65,
10,31,45,82,10258,74VSS
VSS
—
—
—
N/A
N/A
—
15,42,11,30,64,101
44,73
NOTES:
12
The PDSR and PSSR registers are described in the MCF52235 Reference Manual. All programmable signals default to 2mA drive in normal (single-chip) mode.3
All signals have a pull-up in GPIO mode.4The multiplexed CANTX and CANRX signals do not have dedicated pins, but are available as muxed replacements for other signals. 5
For primary and GPIO functions only. 6
Only when JTAG mode is enabled.7For secondary and GPIO functions only.
8RSTI has an internal pull-up resistor, however the use of an external resistor is very strongly recommended 9
For GPIO function. Primary Function has pull-up control within the GPT module This list for power and ground does not include those dedicated power/ground pins included elsewhere, e.g. in the ethernet PHY.
23MCF52235 Family Configurations元器件交易网www.cecb2b.com
MCF52235 Family Configurations
1.5Reset Signals
Table4. Reset Signals
Signal NameReset InReset Out
Abbreviation
RSTIRSTOFunction
Primary reset input to the device. Asserting RSTI immediately resets the CPU and peripherals.
Driven low for 512 CPU clocks after the reset source has deasserted.
I/OIO
Table4 describes signals that are used to either reset the chip or as a reset indication.
1.6PLL and Clock Signals
Table5. PLL and Clock Signals
Signal NameExternal Clock In
CrystalClock Out
Abbreviation
EXTALXTALCLKOUT
Function
Crystal oscillator or external clock input.Crystal oscillator output.
This output signal reflects the internal system clock.
I/OIOO
Table5 describes signals that are used to support the on-chip clock generation circuitry.
1.7Mode Selection
Table6. Mode Selection Signals
Signal NameReset Configuration
Abbreviation
RCONFunction
The Serial Flash Programming mode is entered by asserting the RCON pin (with the TEST pin negated) as the chip comes out of reset. During this mode, the EzPort has access to the Flash memory which can be programmed from an external device.
Reserved for factory testing only and in normal modes of operation should be connected to VSS to prevent unintentional activation of test functions.
II/O
Table6 describes signals used in mode selection, Table6 describes particular clocking modes.
TestTEST
1.8External Interrupt Signals
Table7. External Interrupt Signals
Signal NameExternal Interrupts
AbbreviationIRQ[15:1]External interrupt sources.
Function
I/OI
Table7 describes the external interrupt signals.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 024PreliminaryFreescale Semiconductor元器件交易网www.cecb2b.com
MCF52235 Family Configurations
1.9Queued Serial Peripheral Interface (QSPI)
Table8. Queued Serial Peripheral Interface (QSPI) Signals
Signal NameQSPI Synchronous Serial OutputQSPI Synchronous Serial Data InputQSPI Serial Clock
Abbreviation
Function
I/OOIOO
Table8 describes QSPI signals.
QSPI_DOUTProvides the serial data from the QSPI and can be programmed to be
driven on the rising or falling edge of QSPI_CLK. QSPI_DINQSPI_CLK
Provides the serial data to the QSPI and can be programmed to be sampled on the rising or falling edge of QSPI_CLK.
Provides the serial clock from the QSPI. The polarity and phase of QSPI_CLK are programmable.
Synchronous Peripheral QSPI_CS[3:0]QSPI peripheral chip selects that can be programmed to be active
Chip Selectshigh or low.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
25
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
1.10Fast Ethernet Controller ePHY Signals
Table9 describes the Fast Ethernet Controller (FEC) Signals.
Table9. Fast Ethernet Controller (FEC) Signals
Signal NameTwisted Pair Input +Twisted Pair Input -Twisted Pair Output +Twisted Pair Output -Bias Control Resistor
Abbreviation
RXPRXNTXNTXPRBIAS
Function
Differential Ethernet twisted-pair input pin. This pin is high-impedance out of reset.
Differential Ethernet twisted-pair input pin. This pin is high-impedance out of reset.
Differential Ethernet twisted-pair output pin. This pin is high-impedance out of reset.
Differential Ethernet twisted-pair output pin. This pin is high-impedance out of reset.
Connect a 12.4 kΩ (1.0%) external resistor, RBIAS, between the PHY_RBIAS pin and analog ground.
Place this resistor as near to the chip pin as possible. Stray capacitance must be kept to less than 10 pF
(>50 pF will cause instability). No high-speed signals can be permitted in the region of RBIAS.
Indicates when the ePHY is transmitting or receivingIndicates when the ePHY has a valid linkIndicates the speed of the ePHY connection
Indicates the duplex (full or half) of the ePHY connectionIndicates if the ePHY detects a collisionIndicates if the ePHY is transmittingIndicates if the ePHY is receiving
I/OIIOOI
Activity LEDLink LEDSpeed LEDDuplex LEDCollision LEDTransmit LEDReceive LED
ACT_LEDLINK_LEDSPD_LEDDUPLEDCOLLEDTXLEDRXLED
OOOOOOO
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
26
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
1.11I2C I/O Signals
Table10 describes the I2C serial interface module signals.
Table10. I2C I/O Signals
Signal NameSerial Clock
Abbreviation
SCL
Function
Open-drain clock signal for the for the I2C interface. Either it is driven by the I2C module when the bus is in master mode or it becomes the clock input when the I2C is in slave mode.
Open-drain signal that serves as the data input/output for the I2C interface.
I/OI/O
Serial DataSDAI/O
1.12UART Module Signals
Table11 describes the UART module signals.
Table11. UART Module Signals
Signal NameTransmit Serial Data
Output
AbbreviationUTXDn
Function
Transmitter serial data outputs for the UART modules. The output is held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. Data is shifted out, LSB first, on this pin at the falling edge of the serial clock source.
Receiver serial data inputs for the UART modules. Data is received on this pin LSB first. When the UART clock is stopped for power-down mode, any transition on this pin restarts it.
Indicate to the UART modules that they can begin data transmission.Automatic request-to-send outputs from the UART modules. This signal can also be configured to be asserted and negated as a function of the RxFIFO level.
I/OO
Receive Serial Data
InputClear-to-SendRequest-to-Send
URXDnI
UCTSnURTSn
IO
1.13DMA Timer Signals
Table12 describes the signals of the four DMA timer modules.
Table12. DMA Timer Signals
Signal NameDMA Timer InputDMA Timer Output
Abbreviation
DTINDTOUT
Function
Event input to the DMA timer modules.
Programmable output from the DMA timer modules.
I/OIO
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
27
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
1.14ADC Signals
Table13 describes the signals of the Analog-to-Digital Converter.
Table13. ADC Signals
Signal NameAnalog InputsAnalog Reference
AbbreviationAN[7:0]VRHVRL
Analog Supply
VDDAVSSA
Isolate the ADC circuitry from power supply noise
Function
Inputs to the A-to-D converter.Reference voltage high and low inputs.
I/OIII——
1.15General Purpose Timer Signals
Table14 describes the General Purpose Timer Signals.
Table14. GPT Signals
Signal NameGeneral Purpose Timer Input/Output
AbbreviationGPT[3:0]
Function
Inputs to or outputs from the general purpose timer module
I/OI/O
1.16Pulse Width Modulator Signals
Table15 describes the PWM signals.
Table15. PWM Signals
Signal NamePWM Output Channels
AbbreviationPWM[7:0]
Function
Pulse width modulated output for PWM channels
I/OO
1.17Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and also to interface to the BDMlogic.
Table16. Debug Support Signals
Signal NameJTAG EnableTest ResetTest ClockTest Mode Select
AbbreviationJTAG_ENTRSTTCLKTMS
Function
Select between debug module and JTAG signals at resetThis active-low signal is used to initialize the JTAG logic asynchronously.
Used to synchronize the JTAG logic.
Used to sequence the JTAG state machine. TMS is sampled on the rising edge of TCLK.
I/OIIII
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
28
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
Table16. Debug Support Signals (continued)
Signal NameTest Data InputTest Data Output
Abbreviation
TDITDO
Function
Serial input for test instructions and data. TDI is sampled on the rising edge of TCLK.
Serial output for test instructions and data. TDO is tri-stateable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCLK.
Development Serial Clock-Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication port to the debug module during packet transfers. Maximum frequency is PSTCLK/5. At the synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state.
Breakpoint - Input used to request a manual breakpoint. Assertion of BKPT puts the processor into a halted state after the current instruction completes. Halt status is reflected on processor status signals () as the value 0xF.
Development Serial Input -Internally synchronized input that provides data input for the serial communication port to the debug module, once the DSCLK has been seen as high (logic 1).
Development Serial Output -Provides serial output communication for debug module responses. DSO is registered internally. The output is delayed from the validation of DSCLK high.
Display captured processor data and breakpoint status. The CLKOUT signal can be used by the development system to know when to sample DDATA[3:0].
Processor Status Clock - Delayed version of the processor clock. Its rising edge appears in the center of valid PST and DDATA output. PSTCLK indicates when the development system should sample PST and DDATA values.
If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and PST and DDATA outputs from toggling without disabling triggers. Non-quiescent operation can be reenabled by clearing CSR[PCD], although the external development systems must resynchronize with the PST and DDATA outputs.
PSTCLK starts clocking only when the first non-zero PST value (0xC, 0xD, or 0xF) occurs during system reset exception processing.Indicate core status. Debug mode timing is synchronous with the processor clock; status is unrelated to the current bus transfer. The CLKOUT signal can be used by the development system to know when to sample PST[3:0].Logical “AND” of PST[3.0]
I/OIO
Development Serial
Clock
DSCLKI
BreakpointBKPTI
Development Serial
InputDevelopment Serial
Output
Debug Data
DSII
DSOO
DDATA[3:0]O
Processor Status ClockPSTCLKO
Processor Status
Outputs
PST[3:0]O
All Processor Status
Outputs
ALLPSTO
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
29
元器件交易网www.cecb2b.com
MCF52235 Family Configurations
1.18EzPort Signal Descriptions
Table17 contains a list of EzPort external signals
Table17. EzPort Signal Descriptions
Signal NameEzPort ClockEzPort Chip SelectEzPort Serial Data InEzPort Serial Data Out
AbbreviationEZPCKEZPCSEZPDEZPQ
Function
Shift clock for EzPort transfers
Chip select for signalling the start and end of serial transfers
EZPD is sampled on the rising edge of EZPCK
EZPQ transitions on the falling edge of EZPCK
I/OIIIO
1.19Power and Ground Pins
The pins described in Table18 provide system power and ground to the chip. Multiple pins are providedfor adequate current capability. All power supply pins must have adequate bypass capacitance forhigh-frequency noise suppression.
Table18. Power and Ground Pins
Signal NamePLL Analog Supply
AbbreviationVDDPLL, VSSPLLVDDVSS
Function
Dedicated power supply signals to isolate the sensitive PLL analog circuitry from the normal levels of noise present on the digital power supply.
These pins supply positive power to the core logic.This pin is the negative supply (ground) to the chip.
I/OI
Positive Supply
Ground
I
Some of the VDD and VSS pins on the device are only to be used for noise bypass. Figure4 shows a typicalconnection diagram. Pay particular attention to those pins which show only capacitor connections. Do notconnect power supply voltage directly to these pins.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
30
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
Preliminary Electrical Characteristics
VDDPLLVSSPLLVDDAVRHVRLVSSAVDDRVSSX1
333569707172581110313045447473
0.22µF0.22µF0.1µF0.1µF0.1µF
3.3V
0.1µF
0.1µF
10µF10V
Tantalum
0.22µF
1000pF
*
10µH
MCF52235
VDDX1VDDX2
Pin numbering is shown for the 80-lead TQFP
VSSX2VDD2VSS2VDD1
PHY_RBIASPHY_VDDRXPHY_VDDTXPHY_VDDA48VSS1
465512.4KΩ1%
0.22µF0.22µF0.22µF
49*optional
Figure4. Suggested connection scheme for Power and Ground
2Preliminary Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the MCF52235microcontroller unit. This section contains detailed information on power considerations, DC/ACelectrical characteristics, and AC timing specifications of MCF52235.
The electrical specifications are preliminary and are from previous designs or design simulations. Thesespecifications may not be fully tested or guaranteed at this early stage of the product life cycle, howeverfor production silicon these specifications will be met. Finalized specifications will be published aftercomplete characterization and device qualifications have been completed.
NOTE
The parameters specified in this appendix supersede any values found in themodule specifications.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
31
元器件交易网www.cecb2b.com
Preliminary Electrical Characteristics
2.1Maximum Ratings
Table19. Absolute Maximum Ratings1, 2
Rating
Supply Voltage
Clock Synthesizer Supply VoltageRAM Memory Standby Supply VoltageDigital Input Voltage 3EXTAL pin voltageXTAL pin voltage
Instantaneous Maximum Current
Single pin limit (applies to all pins) 4, 5Operating Temperature Range (Packaged)Storage Temperature Range
SymbolVDDVDDPLLVSTBYVINVEXTALVXTALIDDTA(TL - TH)Tstg
Value– 0.3 to +4.0– 0.3 to +4.0– 0.3 to + 4.0– 0.3 to + 4.00 to 3.3 0 to 3.325– 40 to 85– 65 to 150
UnitVVVVVVmA°C°C
NOTES:
1Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device.2This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD).3Input must be current limited to the I value specified. To determine the value of the required
DD
current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
4All functional non-supply pins are internally clamped to V and V.
SSDD
5Power supply must maintain regulation within operating V range during instantaneous and
DD
operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Insure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power (ex; no clock).Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
32
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
Preliminary Electrical Characteristics
Table20 lists thermal resistance values
Table20. Thermal Characteristics
Characteristic
Junction to ambient, natural convectionJunction to ambient (@200 ft/min)Junction to boardJunction to case
Junction to top of package
Maximum operating junction temperature
112 LQFP
Four layer board (2s2p) 112 LQFP
Four layer board (2s2p) 112LQFP 112LQFPNatural convection 112LQFP
SymbolθJMAθJMAθJBθJCΨjtTj
ValueTBD1,2TBDTBD3TBD4TBD5105
Unit°C / W°C / W°C / W°C / W°C / W
oC
NOTES:1
θJMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of θJmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices.
Conformance to the device junction temperature specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.
2Per JEDEC JESD51-6 with the board horizontal.
3Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.4
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
5Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT.The average chip-junction temperature (TJ) in °C can be obtained from:
TJ=TA+(PD×ΘJMA)(1)
Where:
TAΘJMAPDPINTPI/O
= Ambient Temperature, °C
= Package Thermal Resistance, Junction-to-Ambient, °C/W= PINT + PI/O
= IDD × VDD, Watts - Chip Internal Power
= Power Dissipation on Input and Output Pins — User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
PD=K÷(TJ+273°C)
Solving equations 1 and 2 for K gives:
K = PD × (TA + 273 °C) + ΘJMA × PD 2(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
(2)
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
33
元器件交易网www.cecb2b.com
Preliminary Electrical Characteristics
2.2ESD Protection
Table21. ESD Protection Characteristics1, 2
Characteristics
ESD Target for Human Body ModelESD Target for Machine ModelHBM Circuit DescriptionMM Circuit Description Number of pulses per pin (HBM)positive pulsesnegative pulses
Number of pulses per pin (MM)positive pulsesnegative pulsesInterval of Pulses
SymbolHBMMMRseriesCRseriesC—————
Value20002001500100020011
—
331
secUnitsVVohmspFohmspF—
NOTES:
1All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
2.3
DC Electrical Specifications
Table22. DC Electrical Specifications1
Characteristic
SymbolVDDVIHVILVHYSIinIOZVOHVOLIAPUCin
Min3.00.7 x VDDVSS – 0.30.06 x VDD
–1.0–1.0O VDD - 0.5
__-10——
Max3.64.00.35 x VDD
—1.01.0__0.5- 13077
pF
CL
2550
UnitVVVmVµAµAVVµApF
Supply VoltageInput High VoltageInput Low VoltageInput Hysteresis
Input Leakage Current
Vin = VDD or VSS, Input-only pins
High Impedance (Off-State) Leakage Current
Vin = VDD or VSS, All input/output and output pins Output High Voltage (All input/output and all output pins)IOH = –2.0 mA
Output Low Voltage (All input/output and all output pins)IOL = 2.0mA
Weak Internal Pull Up Device Current, tested at VIL Max.2Input Capacitance 3All input-only pins
All input/output (three-state) pinsLoad Capacitance4Low Drive StrengthHigh Drive Strength
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
34
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
Preliminary Electrical Characteristics
Table22. DC Electrical Specifications (continued)1
Characteristic
Operating Supply Current 5Master ModeWAITDOZESTOP
DC Injection Current 3, 6, 7, 8VNEGCLAMP =VSS– 0.3 V, VPOSCLAMP = VDD + 0.3Single Pin Limit
Total MCU Limit, Includes sum of all stressed pins
1
SymbolIDD
Min————
MaxTBDTBDTBDTBD
UnitmAmAmAµAmA
IIC
-1.0-10
1.010
NOTES:
Refer to Table 23 for additional PLL specifications.2
Refer to the MCF52235 signals chapter for pins having weak internal pull-up devices.3This parameter is characterized before qualification rather than 100% tested.
4pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces require transmission line analysis to determine proper drive strength and termination.
5Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load.
6All functional non-supply pins are internally clamped to V and their respective V.
SSDD
7Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
8Power supply must maintain regulation within operating V range during instantaneous and operating maximum
DD
current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Insure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, system clock is not present during the power-up sequence until the PLL has attained lock.
2.4 Phase Lock Loop Electrical Specifications
Table23. PLL Electrical Specifications
(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V)
Characteristic
PLL Reference Frequency Range1 Crystal reference External referenceSystem Frequency 2External Clock ModeOn-Chip PLL FrequencyLoss of Reference Frequency 3, 5Self Clocked Mode Frequency 4, 5Crystal Start-up Time 5, 6EXTAL Input High VoltageCrystal referenceExternal referenceEXTAL Input Low VoltageCrystal referenceExternal reference
Symbolfref_crystalfref_ext
fsys
Min220fref / 321001—VDD- 1.02.0VSSVSS
Max10.010.0
MHz
60601000510VDDVDD
V
1.00.8
kHzMHzmsVUnitMHz
fLORfSCMtcstVIHEXT
VILEXT
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
35
元器件交易网www.cecb2b.com
Preliminary Electrical Characteristics
Table23. PLL Electrical Specifications (continued)
(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V)
Characteristic
XTAL Output High VoltageIOH = 1.0 mA
XTAL Output Low VoltageIOL = 1.0 mA
XTAL Load Capacitance7PLL Lock Time5,9Power-up To Lock Time 5, 7,8With Crystal ReferenceWithout Crystal ReferenceDuty Cycle of reference 5Frequency un-LOCK RangeFrequency LOCK Range
CLKOUT Period Jitter 5, 6, 8, 9,10, Measured at fSYS MaxPeak-to-peak Jitter (Clock edge to clock edge)Long Term Jitter (Averaged over 2 ms interval)
tlplltlplkSymbolVOLVOL
MinVDD- 1.0—————40- 1.5- 0.75——
Max—
V
0.5—50010.5500601.50.755.01
pFµsmsµs% fsys% fsys% % fsys% fsysUnitV
tdcfULfLCKCjitter
NOTES:
1Input to the PLL is limited to 10MHz max, however the PLL divider can accept up to 40MHz. The input must be divided down to a frequency no greater than 10MHz. This is controlled by register CCHR. 2All internal registers retain data at 0 Hz.
3“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.
4Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR with default MFD/RFD settings.
5This parameter is characterized before qualification rather than 100% tested.6Proper PC board layout procedures must be followed to achieve specifications.
7Load Capacitance determined from crystal manufacturer specifications and will include circuit board parasitics.8Assuming a reference is available at power up, lock time is measured from the time V and V
DDDDPLL are valid to
RSTO negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time must be added to the PLL lock time to determine the total start-up time.
9Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval10
Based on slow system clock of 40 MHz measured at fsys max.
2.5General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, TIMERS, UARTS, FEC, Interrupts and USBinterfaces. When in GPIO mode, the timing specification for these pins is given in Table24 and Figure5.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
36
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
Table24. GPIO Timing
NUMG1G2G3G4
Characteristic
CLKOUT High to GPIO Output ValidCLKOUT High to GPIO Output InvalidGPIO Input Valid to CLKOUT HighCLKOUT High to GPIO Input Invalid
SymboltCHPOVtCHPOItPVCHtCHPI
Min-1.591.5
Max10---Unitnsnsnsns
CLKOUT
G1G2
GPIO Outputs
G3G4
GPIO Inputs
Figure5. GPIO Timing
2.6Reset Timing
Table25. Reset and Configuration Override Timing
(VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1
NUMR1R2R3R4
Characteristic
RSTI Input valid to CLKOUT HighCLKOUT High to RSTI Input invalidRSTI Input valid Time 2CLKOUT High to RSTO Valid SymboltRVCHtCHRItRIVTtCHROV
Min91.55-
Max---10
UnitnsnstCYCns
NOTES:
1All AC timing is shown with respect to 50% O V levels unless otherwise noted.
DD
2During low power STOP, the synchronizers for the RSTI input are bypassed and RSTI is asserted asynchronously to the system. Thus, RSTI must be held a minimum of 100 ns.MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
37
元器件交易网www.cecb2b.com
Preliminary Electrical Characteristics
CLKOUT
1R1R2
R3
R4
R4RSTI
RSTO
Figure6. RSTI and Configuration Override Timing2.7
I2C Input/Output Timing Specifications
Table26. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num 11 I2 I3 I4 I5 I6 I7 I8 I9
Characteristic
Start condition hold timeClock low period
SCL/SDA rise time (VIL=0.5 V to VIH=2.4 V)Data hold time
SCL/SDA fall time (VIH=2.4 V to VIL=0.5 V)Clock high timeData setup time
Start condition setup time (for repeated start condition only)Stop condition setup time
Min2 x tCYC8 x tCYC
—0—4 x tCYC
02 x tCYC2 x tCYC
Max——1—1————
UnitsnsnsmSnsmSnsnsnsns
Table26 lists specifications for the I2C input timing parameters shown in Figure7.
Table27 lists specifications for the I2C output timing parameters shown in Figure7.
Table27. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num 111 I2 1 I3 2 I4 1 I5 3 I6 1 I7 1
Characteristic
Start condition hold timeClock low period
I2C_SCL/I2C_SDA rise time(VIL=0.5 V to VIH=2.4 V)Data hold time
I2C_SCL/I2C_SDA fall time(VIH=2.4 V to VIL=0.5 V)Clock high timeData setup time
Min6 x tCYC10 x tCYC
—7 x tCYC
—10 x tCYC2 x tCYC
Max————3——
UnitsnsnsµSnsnsnsns
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
38
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
Preliminary Electrical Characteristics
Table27. I2C Output Timing Specifications between I2C_SCL and I2C_SDA (continued)
Num I8 1 I9 1
1
Characteristic
Start condition setup time (for repeated start condition only)
Stop condition setup time
Min20 x tCYC10 x tCYC
Max——
Unitsnsns
NOTES:
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR=0x20) results in minimum output timings as shown in Table27. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table27 are minimum values.
2Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up resistor values.
3Specified at a nominal 50-pF load.
Figure7 shows timing for the values in Table26 and Table27.
I2SCLI6I5I1I4I7I8I3I9SDAFigure7. I2C Input/Output Timings
2.8Analog-to-Digital Converter (ADC) Parameters
Table28. ADC Parameters1
Table28 lists specifications for the analog-to-digital converter.
NameVADINRESINLINLDNL
Input voltagesResolution
Integral Non-Linearity (Full input signal range)2Integral Non-Linearity (10% to 90% input signal range)4
Differential Non-LinearityMonotonicity
fADICRAD
ADC internal clockConversion Range
0.1VREFL
Characteristic
MinVREFL12———
Typical——±2.5±2.5-1 < DNL < +1
MaxVREFH12±3±3<+1
UnitVBitsLSB3LSBLSB
GUARANTEED——
5.0VREFH
MHzV
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
39
元器件交易网www.cecb2b.com
Preliminary Electrical Characteristics
Table28. ADC Parameters1 (continued)
NametADPUtRECtADCtADSCADIXINIADIIVREFHVOFFSETEGAINVOFFSETSNRTHDSFDRSINADENOB
Characteristic
ADC power-up time5Recovery from auto standbyConversion timeSample timeInput capacitanceInput impedance
Input injection current7, per pinVREFH current
Offset voltage internal referenceGain Error (transfer path)Offset voltage external referenceSignal-to-Noise ratioTotal Harmonic DistortionSpurious Free Dynamic RangeSignal-to-Noise plus DistortionEffective Number OF Bits
———.99—TBDTBDTBDTBD9.1Min—————
Typical6061TBDTBD—0±111±362 to 66-75756510.6
3—±151.01TBDMax131———
UnittAIC cycles6tAIC cyclestAIC cyclestAIC cycles
pFΩmAµmV—mVdBdBdBdBBits
NOTES:
1All measurements are preliminary pending full characterization, and were made at V = 3.3V, V
DDREFH = 3.3V, and VREFL =
ground
2INL measured from V = V
INREFL to VIN = VREFH
3LSB = Least Significant Bit4INL measured from V = 0.1V
INREFH to VIN = 0.9VREFH
5Includes power-up of ADC and V
REF
6ADC clock cycles
7The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC
2.9DMA Timers Timing Specifications
Table29. Timer Module AC Timing Specifications
NameT1T2
Characteristic 1
DTIN0 / DTIN1 / DTIN2 / DTIN3 cycle timeDTIN0 / DTIN1 / DTIN2 / DTIN3 pulse width
Min3 x tCYC1 x tCYC
Max——
Unitnsns
Table29 lists timer module AC timings.
NOTES:
1All timing references to CLKOUT are given to its rising edge.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
40
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
Preliminary Electrical Characteristics
2.10QSPI Electrical Specifications
Table30 lists QSPI timings.
Table30. QSPI Modules AC Timing Specifications
NameQS1QS2 QS3 QS4QS5
QSPI_CS[3:0] to QSPI_CLK
QSPI_CLK high to QSPI_DOUT valid.
QSPI_CLK high to QSPI_DOUT invalid (Output hold)QSPI_DIN to QSPI_CLK (Input setup)QSPI_DIN to QSPI_CLK (Input hold)
Characteristic Min1—299
Max51010———
UnittCYCnsnsnsns
The values in Table30 correspond to Figure8.
QS1QSPI_CS[3:0]
QSPI_CLK
QS2QSPI_DOUT
QS3QSPI_DIN
QS4QS5Figure8. QSPI Timing
2.11JTAG and Boundary Scan Timing
Table31. JTAG and Boundary Scan Timing
NumJ1J2J3J4J5J6
Characteristics1
TCLK Frequency of OperationTCLK Cycle PeriodTCLK Clock Pulse WidthTCLK Rise and Fall Times
Boundary Scan Input Data Setup Time to TCLK RiseBoundary Scan Input Data Hold Time after TCLK Rise
SymbolfJCYCtJCYCtJCWtJCRFtBSDSTtBSDHT
MinDC4 x tCYC
260426
Max1/4--3--Unitfsys/2nsnsnsnsns
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
41
元器件交易网www.cecb2b.com
Preliminary Electrical Characteristics
Table31. JTAG and Boundary Scan Timing (continued)
NumJ7J8J9J10J11J12J13J14
1
Characteristics1
TCLK Low to Boundary Scan Output Data ValidTCLK Low to Boundary Scan Output High ZTMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise TCLK Low to TDO Data ValidTCLK Low to TDO High ZTRST Assert TimeTRST Setup Time (Negation) to TCLK HighSymboltBSDVtBSDZtTAPBSTtTAPBHTtTDODVtTDODZtTRSTATtTRSTST
Min004100010010
Max3333--268--
Unitnsnsnsnsnsnsnsns
NOTES:
JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
J2
J3
VIHJ4
VIL
J4
J3
TCLK(input)
Figure9. Test Clock Input Timing
TCLK
VIL
J5
VIH
J6
Data Inputs
J7
Input Data Valid
Data Outputs
J8
Output Data Valid
Data Outputs
J7
Data Outputs
Output Data Valid
Figure10. Boundary Scan (JTAG) Timing
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
42
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
Preliminary Electrical Characteristics
TCLK
VIL
J9
VIH
J10
TDITMS
J11Input Data Valid
TDO
J12
Output Data Valid
TDO
J11TDO
Output Data Valid
Figure11. Test Access Port Timing
TCLK
14
TRST13
Figure12. TRST Timing2.12Debug AC Timing Specifications
Table32 lists specifications for the debug AC timing parameters shown in Figure14.
Table32. Debug AC Timing Specification
60 MHz
NumD0D1D2D3 D4 1D5D6D7D8
PSTCLK cycle time
PST, DDATA to CLKOUT setupCLKOUT to PST, DDATA holdDSI-to-DSCLK setupDSCLK-to-DSO holdDSCLK cycle time
BKPT input data setup time to CLKOUT Rise BKPT input data hold time to CLKOUT Rise CLKOUT high to BKPT high Z41.51 x tCYC4 x tCYC5 x tCYC
41.5 0.0
10.0
Characteristic
Min
Max0.5
tCYCnsnsnsnsnsnsnsnsUnits
NOTES:1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
43
元器件交易网www.cecb2b.com
Preliminary Electrical Characteristics
Figure13 shows real-time trace timing for the values in Table32.
CLKOUT
D1D2
PST[3:0]DDATA[3:0]
Figure13. Real-Time Trace AC Timing
Figure14 shows BDM serial port AC timing for the values in Table32.
CLKOUT
D5DSCLK
D3DSICurrent
D4Next
DSOPastCurrent
Figure14. BDM Serial Port AC Timing
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
44
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
Mechanical Outline Drawings
3Mechanical Outline Drawings
This section describes the physical properties of the MCF52235 and its derivatives.
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
45
元器件交易网www.cecb2b.com
Mechanical Outline Drawings
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
46
Preliminary
Freescale Semiconductor
元器件交易网www.cecb2b.com
Mechanical Outline Drawings
MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary
47
元器件交易网www.cecb2b.com
How to Reach Us:
Home Page:
www.freescale.comE-mail:
support@freescale.com
USA/Europe or Locations Not Listed:Freescale Semiconductor
Technical Information Center, CH3701300 N. Alma School RoadChandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130support@freescale.com
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbHTechnical Information CenterSchatzbogen 7
81829 Muenchen, Germany+44 1296 380 456 (English)+46 8 52200080 (English)+49 89 92103 559 (German)+33 1 69 35 48 48 (French)support@freescale.com
Japan:
Freescale Semiconductor Japan Ltd.HeadquartersARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,Tokyo 153-0064, Japan
0120 191014 or +81 3 5437 9125support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.Technical Information Center2 Dai King Street
Tai Po Industrial EstateTai Po, N.T., Hong Kong+800 2666 8080
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution CenterP.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the propertyof their respective owners. The ARM POWERED logo is a registered trademark of ARM Limited. ARM7TDMI-S is a trademark of ARM Limited.Java and all other Java-based marks are trademarks or registeredtrademarks of Sun Microsystems, Inc. in the U.S. and other countries.The Bluetooth trademarks are owned by their proprietor and used by Freescale Semiconductor, Inc. under license.
© Freescale Semiconductor, Inc. 2006. All rights reserved.MCF52235DSRev. 004/2006
因篇幅问题不能全部显示，请点此查看更多更全内容